Pyramid Bumps for Fine-Pitch Chip-Stack Interconnection

Kojima

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 µm/20 µm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.

Section: Introductionsupporting

confidence: 53%

“…To overcome these problems and meet the requirements of 3-D chip stack systems, we have proposed the concept of the compliant bump 6) , such as the pyramid bump. The compliant bump easily deforms and spreads out when pressure is applied to make a bond and hence offers the following characteristics (see Fig.…”

Section: Introductionmentioning

confidence: 99%

Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections

Kojima

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

“…To overcome these problems, we have proposed the compliant bump [8] [9], such as the pyramid bump and cone bump ( Fig. 1).…”

Section: Introductionmentioning

confidence: 99%

Low-Temperature High-Density Chip-Stack Interconnection Using Compliant Bump

2007 Proceedings 57th Electronic Components and Technology Conference

2007

Self Cite

We demonstrate low-temperature high-density chip-stack interconnection using compliant bump. Low temperature chip stacking was carried out by two methods; (1) plasma cleaning of compliant bumps, (2) mechanical caulking using compliant bump and doughnut-shaped electrode. The latter method is very effective in realizing chip stacking even at room temperature. IntroductionThree-dimensional (3D) chip-stacking technology is attracting a great deal of attention for advanced high-speed, compact, and highly functional electronic systems [1]- [7]. The 3D chip stack systems, especially the systems containing the array of circuit elements, such as array sensor, require highly reliable high-density area-bump interconnection technology because they have a large number (> 10,000) of I/0 connections. In solder bump technology, it is difficult to shrink the bump size and pitch. In the non-melting bonding of metal bumps, such as plated Au bumps, bump height deviation induces problems as it causes bonding failure and strain generation in LSI devices when in particular the bump pitch becomes small.To overcome these problems, we have proposed the compliant bump [8] [9], such as the pyramid bump and cone bump (Fig. 1).

“…To overcome these problems and meet the requirements of 3-D chip stack systems, we have proposed the concept of the compliant bump [8] [9], such as the pyramid bump and cone bump (Fig. 1).…”

Section: Introductionmentioning

confidence: 99%

“…Hence the compliant bump offers the following characteristics (see Fig. 2); (1) reliable bonding at low temperature, (2) minimizing the strain generation at the device level [9], (3) suppression of bonding failure [8] [9], and (4) resin exclusion for chip stacking with precoated-resin [8].…”

Section: Introductionmentioning

confidence: 99%

A Large Number of I/O Connections using Compliant Bump

56th Electronic Components and Technology Conference 2006

We demonstrate a large number of I/O connections (number of bumps: 10,000, size/pitch: 10 µm/20 µm) using the compliant bump. The bump connection test was carried out by using not only daisy chain but also active-matrix switch array. These tests revealed that the compliant bump suppresses the bonding failure. We also demonstrate that the compliant bump is very effective in reducing the change in characteristic of MOSFET even when bump bonding is performed directly on the MOSFET.