Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL

Takamaeda-Yamazaki, Shinya

doi:10.1007/978-3-319-16214-0_42

Cited by 124 publications

(34 citation statements)

References 7 publications

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“…The proposed platform was implemented in Python using open source tools [12]. The calculation of the transition probability is based on the TPC script provided by Trust-Hub [10].…”

Section: A Experimental Setupmentioning

confidence: 99%

An Improved Automatic Hardware Trojan Generation Platform

Liu²,

O’Neill

2019

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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Over the past 10 years, various Hardware Trojan (HT) detection techniques have been proposed by the research community. However, the development of HT benchmark suites for testing and evaluating HT detection techniques lags behind. The number of HT-infected circuits available in current public HT benchmarks is somewhat limited and the circuits lack diversity in structure. Therefore, this paper proposes a new method to generate HTs using a highly configurable generation platform based on transition probability. The generation platform is highly configurable in terms of the HT trigger condition, trigger type, payload type and in the number and variety of HT-infected circuits that can be generated. In this research the transition probability of netlists is employed to identify rarely activated internal nodes to target for HT insertion rather than functional simulation as utilised in previous research. The authors believe transition probability provides a more realistic reflection of the netlist activity for use in determining the appropriate position for HT insertion. Finally, the generated HT-infected circuits are tested by a machine learning (ML)-based HT detection technique, which is known as Controllability and Observability for HT Detection (COTD). The resulting false positive and false negative rates illustrate the feasibility of the benchmark suite.

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“…The proposed platform was implemented in Python using open source tools [12]. The calculation of the transition probability is based on the TPC script provided by Trust-Hub [10].…”

Section: A Experimental Setupmentioning

confidence: 99%

An Improved Automatic Hardware Trojan Generation Platform

Liu²,

O’Neill

2019

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…"PyVerilog" [19] is a toolkit of hardware design for Verilog HDL using Python. cReComp uses this toolkit for easy manipulation of Verilog-HDL using Python.…”

Section: Related Workmentioning

confidence: 99%

Automatic Generation Tool of FPGA Components for Robots

Ohkawa

Yamashina

Matsumoto

et al. 2019

IEICE Trans. Inf. & Syst.

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In order to realize intelligent robot system, it is required to process large amount of data input from complex and different kinds of sensors in a short time. FPGA is expected to improve process performance of robots due to better performance per power consumption than high performance CPU, but it has lower development productivity than software. In this paper, we discuss automatic generation of FPGA components for robots. A design tool, developed for easy integration of FPGA into robots, is proposed. The tool named cReComp can automatically convert circuit written in Verilog HDL into a software component compliant to a robot software framework ROS (Robot Operation System), which is the standard in robot development. To evaluate its productivity, we conducted a subject experiment. As a result, we confirmed that the automatic generation is effective to ease the development of FPGA components for robots.

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“…The ADD framework automatically generates a set of files for the entire design, which includes the dataflow core, the input/output streams, and the host interface. This generator is based on the Veriloggen tool . Each dataflow can have an arbitrary number of n inputs and m output streams.…”

Section: Accelerator Design and Deploy ‐ The Add Frameworkmentioning

confidence: 99%

“…This generator is based on the Veriloggen tool. 32 Each dataflow can have an arbitrary number of n inputs and m output streams. ADD generates code to an Intel HPC CPU-FPGA platform, 1 which supports memory communication at 13 GB/s using mixed QPI and PCI channels.…”

Section: Fpga Translation and Accurate Simulationmentioning

confidence: 99%

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Penha

Silva

et al. 2018

Concurrency and Computation

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Summary Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

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Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL

Cited by 124 publications

References 7 publications

An Improved Automatic Hardware Trojan Generation Platform

An Improved Automatic Hardware Trojan Generation Platform

Automatic Generation Tool of FPGA Components for Robots

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

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