QCA circuit design of n ‐bit non‐restoring binary array divider

Non-Restoring Array Divider Using Optimized CAS Cells Based on Quantum-Dot Cellular Automata with Minimized Latency and Power Dissipation for Quantum Computing

“…Recently introduced previous works in [ 20 , 21 ] used a three-input Exclusive-OR (TIEO) gate [ 12 ] to efficiently implement N-RAD designs. However, the robustness of this TIEO gate is not high enough.…”

“…Additionally, in the N-RAD construction period, the pipelining technique in the proposed CAS cell assists it to achieve fewer delays than the best existing ones. A comparison of QCA specifications among designs for the divider is given in Table 4 , and the proposed 3 × 3-bit QCA divider performs better than all of the prior best designs [ 20 , 21 ] in terms of latency.…”

“…In the literature, there have been several prior works on the implementation of QCA-based N-RADs with different techniques [ 17 , 18 , 19 , 20 , 21 ]. For example, the N-RAD divider in [ 17 ] was implemented with a single layer using a clock phase-based wire crossing.…”

“…N-RADs in [ 18 , 19 ] were designed as a multilayer structure based on majority gates and inverters. Recently, a new technical design work has been presented using a cell interaction-based XOR gate in [ 20 , 21 ]. However, these studies also have some limitations in implementation, because propagation delay throughout the wire was not well-considered.…”

“…Combination circuits such as multiplexers and full adders and sequential circuits such as flip-flops, counters, and memories can all be easily implemented visually in accordance with quantum logic [ 6 , 7 , 8 , 9 , 10 ]. Above all, if the structure of an operator such as adder, subtractor, multiplier, divider, and inverter increases, delay time, space complexity, and energy dissipation must be seriously considered in circuit configuration [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 ].…”