QPU-System Co-design for Quantum HPC Accelerators

Quantum Computing Techniques for Multi-Knapsack Problems

“…The circuit runtime also has to be compared to the coherence time of the qubits: while the gate execution times on other platforms such as trapped ions or cold atoms are in general longer than for superconducting QPUs such as the IBM-Q device considered here, those platforms usually also feature longer coherence times. Moreover, realizations based on ions or atoms exhibit better connectivity between the qubits which in turn reduces the amount of gates needed to run the circuit on the QPU and thus also reduces the amount of noise introduced on NISQ-devices [36]. Eventually, the absolute values of the runtimes have to be judged along with the quality of the delivered results within the specific context of the application.…”

“…In order to assess the performance of each quantum algorithm and provide a meaningful comparison with the results from quantum annealing, we estimate the runtimes for standard QAOA and VQE on a quantum processing unit (QPU). A simple model to describe the total runtime T of a variational quantum algorithm is explained in [36] and reads:…”

Co-Design of Quantum Hardware and Algorithms in Nuclear and High Energy Physics

“…The quantum operations are embedded into a classical optimisation loop; after applying the unitary operators to an initial state, the expectation value of the circuit, which represents the problem Hamiltonian and encodes the objective function, is measured. Using a classical optimiser, circuit parameters are changed to minimise the expectation value [4].…”

“…[4], the total execution time for a hybrid algorithm, such as QAOA, comprises several contributions, for instance, circuit execution time, the classical parameter optimisation time, the number of samples required to obtain accurate statistics, or the communication time between the classical computer and the QPU involved. Wintersperger et al [4] compared three different QPU deployment scenarios: (1) having the QPU in the cloud, which is a popular access model for QC vendors, (2) connecting the QPU to the classical CPU via a local bus, and (3) an on-chip QPU-CPU integration. Although the on-chip scenario is associated with the shortest communication time between QPU and CPU, the total execution time improvements over the local bus scenario can be neglected.…”

“…In this contribution, we describe the current state of affairs in QC: currently available noisy intermediate-scale quantum (NISQ) computers suffer from a very limited number of quantum bits, and are subject to considerable imperfections, which narrows their practical computational capabilities. To overcome these limitations, we propose that the co-design [3][4][5][6] of quantum algorithms and hardware is one route towards practical utility: by identifying and developing quantum algorithms and designing special-purpose quantum processing units (QPUs) for specific problems, near-term quantum advantages are likely throughout a variety of domains. We aim to progress towards a joint understanding of requirements, limitations and possibilities throughout the communities of physicists, computer scientists and engineers.…”