Quadratic placement using an improved timing model

Obermeier, Bernd; Johannes, Frank

doi:10.1145/996566.996760

Cited by 7 publications

(5 citation statements)

References 16 publications

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“…Note that some net based timing driven placers not only assign different weights to different nets, but also assign different weights to different segments of the same nets ([6] [5]). Both of our two methods above can work with such placers easily.…”

Section: Increasing Cell Delaysmentioning

confidence: 99%

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Improving voltage assignment by outlier detection and incremental placement

Wu¹,

Wong

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Design for low power has become a key requirement in today's SoC design, especially for mobile applications. Multi-Vdd is an effective method to reduce both leakage and dynamic power. In a multi-Vdd design, cells of different supply voltages are often grouped into a small number of voltage islands, in order to avoid complex power supply system and excessive amount of level shifters. Recently, [9] proposed an elegant algorithm for voltage island grouping based on the physical proximity of the critical cells in a postplacement voltage assignment, and [10] proposed an efficient algorithm for voltage assignment which not only meets timing but also forms good proximity of the critical cells. However, due to insufficient slack, a few isolated critical cells (called outliers) may still exist in the resulting voltage assignment, causing disproportionately expensive penalty to the final voltage island grouping. In this paper, we propose a novel approach to improve the voltage assignment by automatic outlier detection followed by incremental placement. The outlier detection is based on a modified algorithm for the facility location problem. The incremental placement is guided by setting proper constraints on the paths containing the detected outliers, such that the outliers can be eliminated later. Our experiments on industry designs show that our algorithm leads to 12% -54% improvement in the final voltage island grouping, with quick turn around time.

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Section: Increasing Cell Delaysmentioning

confidence: 99%

“…To further improve the result, in future work, we may try more sophisticated schemes, such as setting variable additional net weights according to how far the slack is off the target on each selected path (for nets on different paths), or according to a sensitivity analysis of the net delay (for nets on the same path) [7,5].…”

Section: Additional Notesmentioning

confidence: 99%

Improving voltage assignment by outlier detection and incremental placement

Wu¹,

Wong

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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“…These connection weights are changed in each iteration of global placement in order to model a realistic objective, e.g. timing requirements [26], or routed wirelength, in the quadratic cost function. Hence the more iterations are spent in the global placement, the better is the modeling of the real objective, i.e.…”

Section: Quality Controlmentioning

confidence: 99%

Fast and robust quadratic placement combined with an exact linear net model

Spindler¹,

Johannes²

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Abstract-This paper presents a robust quadratic placement approach, which offers both high-quality placements and excellent computational efficiency. The additional force which distributes the modules on the chip in force-directed quadratic placement is separated into two forces: hold force and move force. Both of these forces are determined without any heuristics. Based on this novel systematic force implementation, we show that our iterative placement algorithm converges to an overlapfree placement. In addition, engineering change order (ECO) is efficiently supported by our placer. To handle the important trade-off between CPU time and placement quality, a deterministic quality control is presented.In addition, a new linear net model is proposed, which accurately models the half-perimeter wirelength (HPWL) in the quadratic cost function of quadratic placement. HPWL in general is a linear metric for netlength and represents an efficient and common estimation for routed wirelength. Compared with the classical clique net model, our linear net model reduces memory usage by 75%, CPU time by 23% and netlength by 8%, which is measured by the HPWL of all nets.Using the ISPD-2005 benchmark suite for comparison, our placer combined with the new linear net model has just 5.9% higher netlength but is 16× faster than APlace, which offers the best netlength in this benchmark. Compared to Capo, our placer has 9.2% lower netlength and is 5.4× faster.In the recent ISPD-2006 placement contest, in which quality is mainly determined by netlength and CPU time, our placer together with the new net model produced excellent results.

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“…• Sophisticated extensions to the proposed method have been developed to meet timing requirements more precisely, e.g. switching to a Steiner-tree model during timingdriven placement [5]. • ECO-capability can be easily implemented by solving equation 7 for e [3].…”

Section: Global Placer Kraftwerkmentioning

confidence: 99%