Quality-Driven SystemC Design

Groe, Daniel; Drechsler, Rolf

doi:10.1007/978-90-481-3631-5

Cited by 43 publications

(9 citation statements)

References 2 publications

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“…To manage the complexity of today's SoCs high-level languages are used for the first models. For this Electronic System Level (ESL) design phase [1] a widely accepted approach is SystemC [2], [3], [4], [5]. Integrated hardware and software models can be developed, exchanged and refined based on the SystemC IEEE standard [6].…”

Section: Introductionmentioning

confidence: 99%

CRAVE: An advanced constrained random verification environment for SystemC

Haedicke

Große

et al. 2012

2012 International Symposium on System on Chip (SoC)

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Abstract-A huge effort is necessary to design and verify complex systems like System-on-Chip. Abstraction-based methodologies have been developed resulting in Electronic System Level (ESL) design. A prominent language for ESL design is SystemC offering different levels of abstraction, interoperability and the creation of very fast models for early software development. For the verification of SystemC models, Constrained Random Verification (CRV) plays a major role. CRV allows to automatically generate simulation scenarios under the control of a set of constraints. Thereby, the generated stimuli are much more likely to hit corner cases. However, the existing SystemC Verification library (SCV), which provides CRV for SystemC models, has several deficiencies limiting the advantages of CRV. In this paper we present CRAVE, an advanced constrained random verification environment for SystemC. New dynamic features, enhanced usability and efficient constraint-solving reduce the user effort and thus improve the verification productivity.

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Section: Introductionmentioning

confidence: 99%

CRAVE: An advanced constrained random verification environment for SystemC

Haedicke

Große

et al. 2012

2012 International Symposium on System on Chip (SoC)

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“…Further techniques called coverage detection exist that can automatically determine whether enough properties have been written, i.e. whether the full input/output behavior is considered by all properties [31]. However, one of the main obstacles remains, i.e.…”

Section: Introductionmentioning

confidence: 99%

Formal Specification Level

Soeken

Drechsler

2015

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“…This strategy was implemented and Electronic System Level (ESL) design emerged [2]. A widely accepted language for ESL design is SystemC [20,14,15,13]. As a C++ class library SystemC perfectly supports abstract modeling, in particular Transaction Level Modeling (TLM) [6,11].…”

Section: Introductionmentioning

confidence: 99%

Simulation-based equivalence checking between SystemC models at different levels of abstraction

Große

Groß

Kühne³

et al. 2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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Today for System-on-Chips (SoCs) companies Electronic System Level (ESL) design is the established approach. Abstraction and standardized communication interfaces based on SystemC Transaction Level Modeling (TLM) have become the core component for ESL design. The abstract models in ESL flows are stepwise refined down to hardware. In this context verification is the major bottleneck: After each refinement step the resulting model is simulated again with the same testbench. The simulation results have to be compared to the previous results to check the functional equivalence of both models. For models at lower levels of abstraction strong approaches exist to formally prove equivalence. However, this is not possible here due to the TLM abstraction. Hence, in practice equivalence checking in ESL flows is based on simulation. Since implementing the necessary verification environment requires a huge effort, we propose an equivalence checking framework in this paper. Our framework allows to easily compare variable accesses in different SystemC models. Therefore, the two models are co-simulated using a client-server architecture. In combination with multi-threading our approach is very efficient as shown by the experiments. In addition, the time required for debugging is reduced by the framework since the respective source code references where the variable accesses did not match are presented to the user.

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Quality-Driven SystemC Design

Cited by 43 publications

References 2 publications

CRAVE: An advanced constrained random verification environment for SystemC

CRAVE: An advanced constrained random verification environment for SystemC

Formal Specification Level

Simulation-based equivalence checking between SystemC models at different levels of abstraction

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