Quality-effective repair of multichip module systems

Park, N.; Meyer, F.J.; Lombardi, Fabrizio

doi:10.1016/s1383-7621(01)00038-8

Cited by 6 publications

(1 citation statement)

References 33 publications

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“…The problem of multiplayer routing has been studied extensively for the printed circuit board and integrated circuit environments [7][8][9][10][11][12][13] . A number of different approaches for multiplayer routing have been described.…”

Section: Introductionmentioning

confidence: 99%

Timing-driven MultiChip Module routing algorithm with crosstalk consideration

Yifeng

Yang

2006

J. of Electron.(China)

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This paper presents a timing-driven MultiChip Module (MCM) routing algorithm considering crosstalk, which maximizes routing density while minimizing vias and total wire length. The routing algorithm allows a more global solution as well as the incorporation of more accurate crosstalk modeling. In addition, various time domain characteristics of MCM are analyzed in this contribution. A deembedding technique for the -parameter S calculation is presented and functions for the time-domain signals are investigated in order to decrease the computation time. Routing results show that the proposed algorithm consistently produces the better results than other previously proposed routers while offering flexibility for future incorporation of noise and delay constraints.

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Section: Introductionmentioning

confidence: 99%

Timing-driven MultiChip Module routing algorithm with crosstalk consideration

Yifeng

Yang

2006

J. of Electron.(China)

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Modeling and Evaluation of Threshold Defect Tolerance

Patitz

Park

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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This paper presents a theoretical study on the threshold defect tolerance level. A new defect level model is proposed and used as a basis for the study in order to facilitate a theoretical modeling and evaluation of defect tolerance under a circumstance in which conventional testing processes are not practically viable. A comprehensive and thorough defect classification and characterization is conducted under specific design constraint when traditional testing is not practically deployable. An approach to an extensive theoretical and parametric compilation and optimization will be introduced in order to reveal a theoretical threshold defect tolerance level at which each choice defect tolerance method and strategy can be justified. The simulation results reveal there exists a theoretical threshold of defect tolerance level that will help guide the test and defect tolerance engineers to identify the optimal and viable testing and defect tolerance level.

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