Quality improvement methods for system-level stimuli generation

Emek, R.; Jaeger, I.; Katz, Yoav; Naveh, Y.

doi:10.1109/iccd.2004.1347923

Cited by 5 publications

(4 citation statements)

References 4 publications

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“…The constraints are extracted from (a) the system architecture and requirements (e.g, a cruising speed must be between 10 and 150 kmph); (b) user requirements for a particular scenario, and (c) "soft" constraints that represent testing knowledge, i.e., the verification expertise which biases test generation towards interesting areas [7]. Thus, a generation of a test can be seen as a solution of a series of CSPs [9].…”

Section: The Test Generatormentioning

confidence: 99%

Using a high-level test generation expert system for testing in-car networks

Adir¹,

Goryachev²,

Greenberg³

et al. 2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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The rising size and complexity of in-car networks call for more advanced and scalable verification solutions. We propose a verification methodology for in-car networks based on a system level test generator tool used for creating massive random biased stimuli, and on coverage and checking monitors. The test generator is an expert system based on an ontology of testing knowledge. A significant challenge is the continuous nature of the stimuli needed to represent the physical environment and the state of the internal components controlled by the vehicle's electronic systems. We report on applying our methodology to an example in-car network simulator.

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Section: The Test Generatormentioning

confidence: 99%

Using a high-level test generation expert system for testing in-car networks

Adir¹,

Goryachev²,

Greenberg³

et al. 2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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“…The paper aims to contribute to the research in the field as the lack of information on competitors' solutions makes it difficult to apply their ideas. The paper summarizes the ideas from different sources [4, 5,6], proposes some important improvements and expresses our vision for organization of a knowledgebase for test generation.…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…IBM Research [3,5,6] has been one of the main contributors in the field of test program generation for microprocessors during the last decades. The first test generation tools were developed in the middle of 1980s.…”

Section: Related Work and Motivationmentioning

confidence: 99%

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A Generic Knowledgebase for Test Generation

Kotsynyak¹,

Tatarnikov²

2014

Proceedings of the Spring/Summer Young Researchers' Colloquium on Software Engineering

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Abstract-Nowadays a lot of various test generation tools are developed and applied to create tests for both software applications and hardware designs. Taking into account the size and complexity of modern projects, there is an urgent need for "smart" tools that would help maximize test coverage and keep the required effort and time to a minimum. Despite the fact that each project is unique in some sense, there is a set of common generation techniques that are applied in a wide range of projects (random tests, combinatorial tests, tests for corner cases, etc). In addition, projects belonging to specific domains tend to share similar test cases or use similar heuristics to generate them. A natural way to improve the quality of testing is to make the most of the experience gained working on different projects or performing testing at different stages of the same project. To achieve this goal, a knowledgebase holding information relevant to test generation would be of a great help. This would facilitate reuse of test cases and generation algorithms and would allow sharing knowledge of "interesting" situations that can occur in a system under test. The paper proposes a concept of a knowledgebase for test generation that can be used in a wide range of test generation tools. At ISPRAS, it is applied in test program generation tools that create test programs for microprocessors. The knowledgebase is designed to store information on widely used test generation techniques and test situations that can occur in a microprocessor design under verification.

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