Quality improvement of metalorganic chemical vapor deposition grown GaP on Si by AsH3 preflow

Abstract

GaP epilayers are grown on Si substrates after AsH3 preflow. Electron beam induced current observation and double-crystal x-ray diffraction show that the AsH3 preflow drastically improves crystalline quality of GaP epilayers. The full width at half-maximum of the (400) reflection obtained from 4.8 μm GaP is as small as 115 arcseconds. Secondary ion mass spectroscopy shows that As atoms accumulate at the GaP/Si interfaces, playing an important role in preventing Si outdiffusion into the GaP epilayers.

Effect of two-step growth process on structural, optical and electrical properties of MOVPE-grown GaP/Si

“…Hereafter, we discuss important results for the sample S3. This FWHM value (0.091) of S3 is relatively small when compared with that of the reported GaP layer (similar thickness) grown by the same technique [21]. The f scan over 3601 azimuths for (11 5) reflection shows only four distinct peaks separated by 901 intervals, which confirms the single crystalline nature of GaP layers.…”

Studies on MOVPE growth of GaP epitaxial layer on Si(001) substrate and effects of annealing

“…We have also calculated the E 0 (G 1c -G 15v ) $2.78 eV for GaP epilayer grown on Si substrates from SPV results which is not possible either form transmission or PL measurements. It is to be noted that the crystalline quality of the layer grown using MOVPE with similar thickness, the FWHM is more when compared with these annealed epilayer [16]. Hence the GaP/Si-based heterostructure can be made with appropriate MOVPE growth and annealing conditions, which could be used in many optoelectronic applications.…”

Investigation of heteroepitaxy on nanoscopically roughened (001)Si by real‐time spectroscopic polarimetry

“…We are currently modifying the system configuration to accomplish this. Although growth of GaP on Si is challenging, several groups have reported results of varying crystal quality [1][2][3][11][12][13][14][15][16]. A universal procedure is to heat the Si substrates to 900 to 1180 °C for intervals of the order of minutes, with the presumed objective of removing residual oxides.…”

“…However, the associated chemical incompatibility causes formidable difficulties, especially charge discontinuity at the heteroepitaxial interface and three-dimensional III-V growth as a result of low densities of nucleation sites and long surface diffusion lengths. Many attempts have been made to overcome these problems, including two-step growth [1,2], preflow by more reactive species [3], use of buffer layers [4] and/or unconventional orientations [5], ion-assisted deposition [6], and growth on patterned substrates [7]. The failure to realize the heteroepitaxial growth of electronic-grade III-V materials on Si is generally attributed to the factors mentioned above.…”