Quantified Synthesis of Reversible Logic

2010 40th IEEE International Symposium on Multiple-Valued Logic

2010

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In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work and generates a cascade of inverted-control-Toffoli gates from the ESOP representation of a multi-output function. The algorithm first generates a circuit with n + m lines, where n and m are the number of inputs and outputs, respectively. A set of gate transformations are applied to the circuits to remove some of the output lines. The improvements of this new algorithm are twofold: most NOT gates are eliminated and the number of lines is reduced. A significant reduction is the quantum cost of the resulting networks can be observed.

Section: Introductionmentioning

confidence: 99%

ESOP-Based Toffoli Network Generation with Transformations

Sanaee

2010 40th IEEE International Symposium on Multiple-Valued Logic

2010

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“…Reversible synthesis algorithms work with various kinds of logic representations such as: truth table [8], Positive Polarity Reed-Muller expressions (PPRM) [4], EXOR Sum of Products (ESOP) [2], SharedPPRM (SBDD) [12], and Binary Decision Diagrams (BDDs) [15].…”

Section: Introductionmentioning

confidence: 99%

Generating Toffoli networks from ESOP expressions

Sanaee

2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing

2009

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In this paper a new heuristic ESOP-based synthesis method for Toffoli networks is proposed. This synthesis method takes advantage of the shared-ESOP cubes among the outputs to generate a cascade of Toffoli gates. The method is suitable to generate circuits for functions with large number of input variables. A greedy approach is utilized to select pairs among the different outputs with common ESOP-cubes. The shared terms need only to be realized once and the result can then be transferred to the second output, and thus reducing the number of Toffoli gates. The synthesis algorithm has been applied to a set of benchmark functions. Experimental results show that the algorithm can generate circuits with reduced quantum cost for virtually all functions. Template applications can further improve the results.

“…Exact synthesis for all three variables functions can be obtained by enumeration [13]. Algorithms based on Boolean Satisfiability Techniques (SAT) can find exact solutions for some functions with up to five variables [14][15][16]. A limiting factor is also the number of gates in the exact solutionfunctions with more than ten gates can normally not be minimised.…”

Section: Synthesis Problemmentioning

confidence: 99%

Challenges and advances in Toffoli network optimisation

IET Computers & Digital Techniques

2014

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This study gives a brief overview of the current trends in reversible logic synthesis with emphasis on template matching. The basic building block for reversible circuits considered here is the multiple-control Toffoli gate. Some approaches to synthesis are reviewed and the challenges are explained. Since many practical functions are not reversible, they must be embedded into reversible ones, if they are to be implemented using reversible logic. The complexity of such embeddings is expounded. A two phase synthesis is described where particular attention is devoted to the optimisation phase via template matching. Insights into the properties of the templates, have led to algorithms that aid the generation of templates. Until recently, the application of templates has been guided by different heuristics. A review of an exact template matching algorithm with a discussion of the implications of such an algorithm is given. Exact matching affects both the generation as well as the application of templates. Results from a prototype implementation are encouraging.