Quantifying the impact of optical interconnect latency on the performance of optoelectronic FPGAs

Dambre, Joni; Marck, Herwig Van; Campenhout, J. Van

doi:10.1109/pi.1999.806399

Cited by 8 publications

(4 citation statements)

References 13 publications

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“…• The average interconnection length is smaller because the distance between the neighboring FPGAs is reduced [57]. According to [63], in a 2D planar MFS platform, the nominal PCB trace length for pointto-point data signal transmission in DDR mode is 6-7 inches, resulting in a propagation delay of hundreds of picoseconds.…”

Section: Previous Research On Mfs Serial Optical Interfacementioning

confidence: 99%

“…The small and equal delay values between FPGA pairs enabled high speed data transfer, because it allowed wave-pipeline based pin multiplexing. The author mapped 1000 randomly generated design scenarios automatically on the structure and compared the achievable system prototyping speed with a group of alternative concepts.Dambre[57] addressed the performance advantage of using optoelectronic area-I/O to realize 3D MFS architectures. The authors used minimum achievable system clock period as an evaluation metric by implementing limited set of synchronous designs.…”

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confidence: 99%

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Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures

Kashif

Khalid

2016

2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)

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I certify that I have obtained a written permission from the copyright owner(s) to include the above published material(s) in my thesis. I certify that the above material describes work completed during my registration as a graduate student at the University of Windsor. I certify that, to the best of my knowledge, my thesis does not infringe upon anyone's copyright nor violate any proprietary rights and that any ideas, techniques, quotations, or any other material from the work of other people included in my thesis, published or otherwise, are fully acknowledged in accordance with the standard referencing practices. Furthermore, to the extent that I have included copyrighted material that surpasses the bounds of fair dealing within the meaning of the Canada Copyright Act, I certify that I have obtained a written permission from the copyright owner(s) to include iv such material(s) in my thesis and have included copies of such copyright clearances to my appendix. I declare that this is a true copy of my thesis, including any final revisions, as approved by my thesis committee and the Graduate Studies office, and that this thesis has not been submitted for a higher degree to any other University or Institution.

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Section: Previous Research On Mfs Serial Optical Interfacementioning

confidence: 99%

mentioning

confidence: 99%

Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures

Kashif

Khalid

2016

2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…3-10 ns) [10,11]. The latency of the electronic-optical conversions has been investigated by Dambre et al [12] and has been found to be of the order of 5-10 ns using state-of-the-art components according to the Technology Roadmap [3], which is commensurate with experimental results obtained at Heriot-Watt [9]. This gives an estimated L SPA value of 8-20 ns, resulting in a worst-case estimate of,…”

Section: Smart-pixel Layermentioning

confidence: 99%

Supporting Bulk Synchronous Parallelism with a high‐bandwidth optical interconnect

Gourlay

Dew

Djemame

et al. 2004

Concurrency and Computation

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SUMMARYThe list of applications requiring high-performance computing resources is constantly growing. The cost of inter-processor communication is critical in determining the performance of massively parallel computing systems for many of these applications. This paper considers the feasibility of a commodity processorbased system which uses a free-space optical interconnect. A novel architecture, based on this technology, is presented. Analytical and simulation results based on an implementation of BSP (Bulk Synchronous Parallelism) are presented, indicating that a significant performance enhancement, over architectures using conventional interconnect technology, is possible.

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“…Latency is very important in optical interconnects as mentioned by Dambre et al [8], who show that with low latency optical links, three-dimensional (3-D) optoelectronic multi-FPGAs outperform two-dimensional (2-D) electronic FPGAs. Also, recently Collet et al [9] concluded that since the most critical issue in computer architecture is the access time to the main memory, signal latency is of critical importance in implementing optical interconnects.…”

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confidence: 99%

Latency reduction in optical interconnects using short optical pulses

Agarwal

Keeler

Nelson

et al. 2003

IEEE J. Select. Topics Quantum Electron.

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We present a new method of latency reduction in optical interconnects: using very low duty cycle return-to-zero encoding (i.e., subpicosecond pulses). An analytical comparison of three different receiver architectures, including transimpedance, integrating, and totem-pole diode pair, is presented. For all three receivers, we demonstrate that using short pulses instead of nonreturn-to-zero (NRZ) shortens the circuit delay. We also experimentally demonstrate a 65% reduction in latency of a transimpedance receiver by using short optical pulses. Finally, we show that the latency of optical interconnects can be comparable to or even less than electrical interconnects for global on-chip communication. Index Terms-Complementary metal-oxide-semiconductor (CMOS) integrated circuits, integrating receivers, latency, multiple quantum well (MQW) modulator, optical interconnects, short optical pulses, totem-pole diode pair, trans-impedance receivers. I. INTRODUCTION M ODERN computer processors run at the clock speeds of many gigahertz but the processor to memory interface typically runs at only a few hundred megahertz. A key reason for this difference, and a problem for computing in general, is that the interface connection speeds are not able to keep up with the increase in the processor speeds. This is mainly because of design issues of electrical busses and their underlying physical properties. Due to the capacity limitations of electrical wires, most long distance communication is now done via optics. For medium distance communication, e.g., local-area network (LAN), metropolitan area networks (MAN), wide area network (WAN) (about 300 m-100 km), optics is making inroads, specifically, because only optics can support the high data rates required by these applications. At shorter distances (a few meters-few hundred meters), primarily in data links, optics is rapidly gaining entry. Recently, a lot of research has been done Manuscript

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Quantifying the impact of optical interconnect latency on the performance of optoelectronic FPGAs

Cited by 8 publications

References 13 publications

Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures

Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures

Supporting Bulk Synchronous Parallelism with a high‐bandwidth optical interconnect

Latency reduction in optical interconnects using short optical pulses

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