Quantitative analysis of State-of-the-Art synchronizers: Clock domain crossing perspective

Sharif, N.; Ramzan, Nadra; Khalid, Faiq; Hasan, Osman; Hasan, Syed Rafay

doi:10.1109/icet.2011.6048485

Cited by 8 publications

(1 citation statement)

References 9 publications

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“…For clock domain crossing (CDC) paths we do not have to add a literal as we assume that multiple clock domain designs are implemented using asynchronous FIFOs or multi-flop synchronizers [8]. These synchronizers contain minimal or no combinational logic, which would not substantially impact the solving time.…”

Section: A Optimizing Performancementioning

confidence: 99%

Multiple clock domain synchronization in a QBF-based verification environment

Maksimovic

Veneris

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Modern designs are growing in size and complexity, becoming increasingly harder to verify. Today, they are architected to include multiple clock domains as a measure to reduce power consumption. Verifying them proves to be a computationally intensive and challenging task as it requires their clocks to be synchronized. To achieve synchronization, existing Boolean satisfiability-based methodologies add hardware to combine the clock domains before transforming them into their iterative logic array representation (ILA). As a consequence, this results in the addition of redundant time-frames adding overhead during verification. This paper introduces a novel framework to verify designs with multiple clocks using Quantified Boolean Formula satisfiability (QBF). We first present a formulation that models an ILA representation with symbolic universal quantification to achieve synchronization. This is later extended with the use of a clock divider to overcome inefficiencies. The net effect is the reduction in the number of redundant time-frames. Furthermore, the usage of QBF results in significant memory savings when compared to traditional methods. Experiments on bounded model checking demonstrate memory reductions of 76% on average with competitive run-time performance.

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Section: A Optimizing Performancementioning

confidence: 99%

Multiple clock domain synchronization in a QBF-based verification environment

Maksimovic

Veneris

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Runtime hardware Trojan monitors through modeling burst mode communication using formal verification

Khalid

Hasan

et al. 2018

Integration

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Timing variation aware dynamic digital phase detector for low‐latency clock domain crossing

Khalid

Hasan

Sharif

et al. 2014

IET Circuits, Devices & Systems

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This study presents a digital phase detector-based approach for estimating and synchronising phase variations between clock domains. Instead of waiting for the resolution of metastability (with finite probability of failure), the authors propose a metastability avoidance algorithm, based on a sampling method for asynchronous signals. The results, using 90 nm inovation for high performance microelectronics (IHP) technology, show that the proposed design is about 1.5 times faster and provides a 35% improvement in Energy-Delay Product compared with the state-of-the-art approaches. Moreover, it completely prevents metastability failures.

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Quantitative analysis of State-of-the-Art synchronizers: Clock domain crossing perspective

Cited by 8 publications

References 9 publications

Multiple clock domain synchronization in a QBF-based verification environment

Multiple clock domain synchronization in a QBF-based verification environment

Runtime hardware Trojan monitors through modeling burst mode communication using formal verification

Timing variation aware dynamic digital phase detector for low‐latency clock domain crossing

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