2021
DOI: 10.1088/1361-6641/abd15b
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Quantitative evaluation of process-induced line-edge roughness in FinFET: Bayesian regression model

Abstract: With the aggressive scaling down of the minimum feature size of advanced metal–oxide–semiconductor devices, it has become imperative to design and fabricate process-variation-immune devices. Technology computer-aided design simulations are typically used to test thousands of devices for process-variation immunity, but the process is computationally expensive. In this work, we propose a novel approach to simulate and predict the current–voltage characteristics of fin field-effect transistor devices with process… Show more

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Cited by 2 publications
(3 citation statements)
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“…The overall prediction performance was improved, as compared against the previous work [1] which is the Bayesian linear regression (BLR) model (see Table II). Note that the HS-BNN model for this comparison is only for the FinFET with Lg = 14 nm, Wfin = 7 nm, Hfin = 30 nm because the BLR model made predictions only for the corresponding FinFET structure.…”
Section: Resultsmentioning
confidence: 92%
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“…The overall prediction performance was improved, as compared against the previous work [1] which is the Bayesian linear regression (BLR) model (see Table II). Note that the HS-BNN model for this comparison is only for the FinFET with Lg = 14 nm, Wfin = 7 nm, Hfin = 30 nm because the BLR model made predictions only for the corresponding FinFET structure.…”
Section: Resultsmentioning
confidence: 92%
“…As mentioned in the previous study [1], the distribution of 𝑙𝑜𝑔(𝐼 𝐷𝑆 ) for a given 𝑉 𝐺𝑆 can be considered as a normal distribution in terms of small kurtosis and skewness values. From this perspective, the mean and standard deviation of 𝑙𝑜𝑔(𝐼 𝐷𝑆 ) (denoted as 𝜇𝐼 𝐷𝑆 and 𝜎𝐼 𝐷𝑆 , respectively) were selected as target variables.…”
Section: Simulation Methodology and Data Preparationmentioning
confidence: 99%
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