Quantitative Performance Evaluation of Uncertainty-Aware Hybrid AADL Designs Using Statistical Model Checking

Bao, Yongxiang; Chen, Mingsong; Zhu, Qi; Wei, Tongquan; Mallet, Frédéric; Zhou, Tao

doi:10.1109/tcad.2017.2681076

Cited by 20 publications

(13 citation statements)

References 21 publications

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“…Formal modeling is applied in 95% of the studies and formal veriication in 67%. Model checking is the most commonly adopted technique (47%) [9,15,20,35,37,38,41,47,64,82,87,91,96,116,117,128], followed by simulation (27%) [9,15,20,36,41,57,64,82,96,116,117,124], theorem proving (19.5%) [14,41,68,72,84] and reinement (18%) [7,37,68,81,82,84,91,96,116]. Less commonly used techniques are those strictly related to code, like test generation (6%) [31,64,124], code generation (6%) [7,14,62,...…”

Section: Summary and Discussionmentioning

confidence: 99%

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Formal Methods in Railways: A Systematic Mapping Study

Ferrari¹,

Beek

2022

ACM Comput. Surv.

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Formal methods are mathematically based techniques for the rigorous development of software-intensive systems. The railway signaling domain is a field in which formal methods have traditionally been applied, with several success stories. This article reports on a mapping study that surveys the landscape of research on applications of formal methods to the development of railway systems. Following the guidelines of systematic reviews, we identify 328 relevant primary studies, and extract information about their demographics, the characteristics of formal methods used and railway-specific aspects. Our main results are as follows: (i) we identify a total of 328 primary studies relevant to our scope published between 1989 and 2020, of which 44% published during the last 5 years and 24% involving industry; (ii) the majority of studies are evaluated through Examples (41%) and Experience Reports (38%), while full-fledged Case Studies are limited (1.5%); (iii) Model checking is the most commonly adopted technique (47%), followed by simulation (27%) and theorem proving (19.5%); (iv) the dominant languages are UML (18%) and B (15%), while frequently used tools are ProB (9%), NuSMV (8%) and UPPAAL (7%); however, a diverse landscape of languages and tools is employed; (v) the majority of systems are interlocking products (40%), followed by models of high-level control logic (27%); (vi) most of the studies focus on the Architecture (66%) and Detailed Design (45%) development phases. Based on these findings, we highlight current research gaps and expected actions. In particular, the need to focus on more empirically sound research methods, such as Case Studies and Controlled Experiments, and to lower the degree of abstraction, by applying formal methods and tools to development phases that are closer to software development. Our study contributes with an empirically based perspective on the future of research and practice in formal methods applications for railways. It can be used by formal methods researchers to better focus their scientific inquiries, and by railway practitioners for an improved understanding of the interplay between formal methods and their specific application domain.

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Section: Summary and Discussionmentioning

confidence: 99%

“…A large variety of modeling language families and tools is used. The dominant languages are UML (18%) [21,35,37,38,81,116,128] and B (15%) [1,7,14,41,68,82,91,96,116], while frequently used tools are ProB (9%) [1,41,82,91,96,116], NuSMV (8%) [35,37,38] and UPPAAL (7%) [9,124].…”

Section: Summary and Discussionmentioning

confidence: 99%

Formal Methods in Railways: A Systematic Mapping Study

Ferrari¹,

Beek

2022

ACM Comput. Surv.

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“…However, those time extensions deal (similar to the aforementioned UML profile [23]) with time aspects relevant for real-time scheduling. Bao et al present an AADL annex for the specification of uncertainty [30]. While their approach enables modeling of uncertainty w.r.t.…”

Section: Related Workmentioning

confidence: 99%

A Domain-Specific Language for Modeling and Analyzing Solution Spaces for Technology Roadmapping

Breckel¹,

Pietron²,

Juhnke³

et al. 2021

Preprint

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“…Bao et al [31] present the Uncertainty annex, which is a proposed extension language to AADL. They transform the uncertain-aware Hybrid AADL to NPTA and present a verification based on the UPPAAL-SMC.…”

Section: Related Workmentioning

confidence: 99%

Formal Verification of AADL Models by Event-B

Hadad

Ahmed

2020

IEEE Access

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AADL is widely used to depict the architecture and behavior of real-time safety-critical systems such as avionics and aerospace. The development of these systems has strict requirements for building fault-free systems. Formal verification is frequently applied to verify the critical properties of the systems, such as safety and liveness; however, the formal verification is not supported by AADL. Model transformation is commonly applied to provide formal semantics; hence, the AADL model can be verified by a language that supports formal verification in addition to the ability to cover all AADL model behavior. Event-B, with its proof obligation, is increasingly used to model and verify safety-critical systems. This paper presents the transformation of the AADL model into Event-B, which captures most AADL components and behavioral actions to be effective in the verification of current real-time systems models. Then, we define theorems and invariants of safety and liveness properties to be proven by using the RODIN platform. To demonstrate the efficacy of our method, we model the AADL of movement authority (MA) control of the Chinese Train Control System, transform the AADL model to Event-B and verify its crucial properties.

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Quantitative Performance Evaluation of Uncertainty-Aware Hybrid AADL Designs Using Statistical Model Checking

Cited by 20 publications

References 21 publications

Formal Methods in Railways: A Systematic Mapping Study

Formal Methods in Railways: A Systematic Mapping Study

A Domain-Specific Language for Modeling and Analyzing Solution Spaces for Technology Roadmapping

Formal Verification of AADL Models by Event-B

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