Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect

Abstract

Capacitive and inductive crosstalk noises are expected to be more serious in advanced technologies. However, capacitive and inductive crosstalk noises in the future have not been concurrently and sufficiently discussed quantitatively, though capacitive crosstalk noise has been intensively studied solely as a primary factor of interconnect delay variation. This paper quantitatively predicts the impact of capacitive and inductive crosstalk in prospective processes, and reveals that interconnect scaling strategies strongly affect relative dominance between capacitive and inductive coupling. Our prediction also makes the point that the interconnect resistance significantly influences both inductive coupling noise and propagation delay. We then evaluate a tradeoff between wire cross-sectional area and worst-case propagation delay focusing on inductive coupling noise, and show that an appropriate selection of wire cross-section can reduce delay uncertainty at the small sacrifice of propagation delay.

A unified system level error model of crosstalk and electromigration for on-chip interconnect

“…The noise sources for the proposed model of this paper are crosstalk and EM (electromigration). Due to high coupling to ground capacitance ratio, and packed interconnect wires, coupling capacitance has become a major noise source, particularly in long interconnect [2,3]. The induced crosstalk causes glitch and delay noises which can result in signal integrity problems or timing errors.…”