Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms

Jing, Naifeng; Lee, Ju-Yueh; Feng, Zhe; He, Wenqi; Mao, Zhigang; Wen, Shi-Jie; Wong, Rick; He, Lei

doi:10.1109/fpl.2011.57

Cited by 13 publications

(8 citation statements)

References 12 publications

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“…The column "Chip failure rate" signifies the failure rate when SEUs occur on both LUT configuration bits and interconnect configuration bits. The evaluation of interconnect soft errors is based on another work [16], which applies logic simulation to a post-layout FPGA application, targeting the unidirectional routing in the modern FPGAs.…”

Section: Resultsmentioning

confidence: 99%

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

Feng

Jing

Chen

et al. 2011

2011 21st International Conference on Field Programmable Logic and Applications

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Abstract-SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chiplevel MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm.

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Section: Resultsmentioning

confidence: 99%

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

Feng

Jing

Chen

et al. 2011

2011 21st International Conference on Field Programmable Logic and Applications

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“…Each MUX is typically configured by several encoded configuration bits (CRAM bits), which contribute to the majority of the CRAM bits in FPGA. For example, we observe that interconnects contribute to nearly 80% of the CRAM bits for the 10 largest MCNC benchmarks when they are synthesized to the minimum FPGA dimensions with 6-input LUTs [12].…”

Section: A Fpga Architecture and Interconnect Faultmentioning

confidence: 99%

Mitigating FPGA interconnect soft errors by in-place LUT inversion

Jing¹,

Lee²,

He³

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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-Modern SRAM-based FPGAs (Field Programmable Gate Arrays) use multiplexer-based unidirectional routing, and SRAM configuration cells in these multiplexers contribute to the majority of soft errors in FPGAs. In this paper, we formulate an In-Placed inVersion (IPV) on LUT (Look-Up Table) logic polarities to reduce the Soft Error Rate (SER) at chip level, and reveal a locality and NP-Hardness of the IPV problem. We then develop an exact algorithm based on the binary integer linear programming (ILP) and also a heuristic based on the simulated annealing (SA), both enabled by the locality. We report the results for 10 largest MCNC combinational benchmarks synthesized by ABC and then placed and routed by VPR. The results show that IPV obtains close to 4x chip level SER reduction on average and SA is highly effective by obtaining the same SER reduction as ILP does. In addition, IPV does not change placement and routing, and does not affect design closure. To the best of our knowledge, it is the first in-depth study on SER reduction for modern multiplexer-based FPGA routing by in-placed logic re-synthesis.

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“…RELATED WORK Previous research has studied the impact of SEUs on SRAM FPGA devices [3], [6], [11]. Many techniques have been proposed to provide highly reliable FPGA devices, e.g., radiation-hardened FPGAs [20], [21], to lower the effect of radiation-induced SEUs.…”

Section: Introductionmentioning

confidence: 99%

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning

Schmidt

Ziener

Teich

2014

2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops

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Existing techniques for SEU mitigation on FPGAs by scrubbing do not prevent permanent malfunction of a circuit design in case that the corresponding configuration bits do belong to feedback loops. In this paper, we a) provide a circuit analysis technique to distinguish so-called critical bits from essential bits to determine which parts of a bitstream will need also staterestoring actions after scrubbing and which not. Moreover, b) we will propose floorplanning techniques to reduce the effective number of frames that need to be scrubbed and c), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the MeanTime-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapathintensive circuits may be reduced by up to 48.5 % in comparison to a standard approach. For the MTTR calculation, we assume a system with checkpointing using the Xilinx SEM IP core to implement the scrubbing controller.

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Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms

Cited by 13 publications

References 12 publications

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

Mitigating FPGA interconnect soft errors by in-place LUT inversion

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning

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