Quantization analysis tool for fixed-point implementation of real time algorithms on the TMS320C5000

Kamath, Sanmati; Magotra, N.; Shrivastava, Ashish

doi:10.1109/icassp.2002.5745480

Cited by 6 publications

(1 citation statement)

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“…The TMS320C55x digital signal processor (DSP) represents the latest generation of 'C5000 DSPs from Texas Instruments. The 'C55x is optimized for power efficiency, low system cost, and best-in-class performance for tight power budgets [2] [3]. The 'C55x core's low power dissipation is achieved through high levels of power-down configurability and granularity coupled with power management that occurs automatically and is transparent to the user.…”

Section: Architectural Levelmentioning

confidence: 99%

Energy efficient Digital Signal Processing

Magotra

Larimer

2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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This paper focuses on issues related to energy efficient Digital Signal Processing (DSP) -taking a Systemsto-Silicon approach. This implies that achieving maximum energy efficiency in a DSP system is a distributed task from the systems level (compilers, algorithm design etc.) to a silicon (transistor, process technologies etc.) level. It addresses how we view this problem and also uses specific application areas such as hearing devices and medical imaging to illustrate the needs and concepts involved in this context.

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Section: Architectural Levelmentioning

confidence: 99%

Energy efficient Digital Signal Processing

Magotra

Larimer

2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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Energy efficient DSP systems - architecture and algorithms issues

Magotra

Siravara

Larimer

Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.

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This paper presents some insights into the architecture of one o f Texas Instrument's (TI) most energy efficient Digital Signal Processor's (DSP), the TMS320C55x. It discusses key low-power architecture issues including the rationale used in making trade-offs that did not adversely affect performance while minimizing chip level power requirements. The paper also discusses some algorithm development centric issues to illustrate how algorithm level researchers can also contribute to the bottom line when it comes to decreasing power consumption o f a DSP system.

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