Quantum Dot Cellular Automata-Based Design of 4 × 4 TKG Gate and Multiplier with Energy Dissipation Analysis

Bhat, Soha Maqbool; Ahmed, Suhaib; Kakkar, Vipan

doi:10.1007/978-981-16-8892-8_61

Cited by 1 publication

(2 citation statements)

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“…The clocking scheme in QCA is shown in fig. 3 in which clock zone are represented with different colors, the input cell is marked with yellow color and the output cell is marked with blue color [24][25]. In this section, we'll discuss newly proposed designs of a Half Adder, 2×2 VM, 4-bit RCA, 4×4 VM and 8×8 VM and will also investigate why these proposed designs are superior than their previous counterparts.…”

Section: A Majority Gate Logicmentioning

confidence: 99%

“…Likewise, to execute the multiplication of a 16x16 Vedic Multiplier using a conventional formula, the architecture involves utilizing four 8x8 multipliers, a 16-bit Ripple Carry Adder (RCA) (one number), a 16-bit Full Adder (FA) (one number), and a 7-bit Ripple Carry Adder(RCA) (one number). The different components within the multiplier employ a traditional formula to determine parameters such as the count of majority gates and inverters used [24].In the 4x4 Vedic multiplier, there are seven full adders, nine half adders, and sixteen ANDgates. Each adder consists of two majority gates and one inverter.…”

Section: F Proposed Conventional Formula For Nn Vedic Multipliermentioning

confidence: 99%

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Cell Optimization and Realization of Vedic Multiplier Desing in QCA

Kirti Singh,

Wairya,

Tripathi

2023

IJCDS

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The construction of devices with smaller sizes, lower power dissipation, and higher speeds is a significant problem in contemporary computational technology. Technology advancement is required to get improved power dissipation, size, and speed optimization. By incorporating numerous architectural and behavioural alterations in the current technologies, researchers are attempting to identify ways and means. Designing digital circuits based on reversible logic and implementing them in quantum cellular automata is one such potential approach (QCA). The propagation delay in a multiplication operation is mostly caused by the addition of partial products and the production of partial products. This study proposes a Vedic multiplier based on UrdhwaTriyakbhyam. It has been found that the suggested designs of a Half Adder, 4-bit Ripple Carry Adder, 2×2 Vedic Multiplier, followed by 4×4 Vedic Multiplier and 8×8 Vedic Multiplier circuits have resulted in reductions of 68.75%, 72.64%, 44.84%, 43.44%, and 60.00% in the circuit size, respectively. When compared to previously proposed circuits, improvements in the area have also been observed, with increases of 57.14%, 55.55%, 48.45%, 28.03%, and 42.57% in the area of the Half Adder Circuit, 2×2 Vedic Multiplier, 4-bit Ripple Carry Adder, 4×4 Vedic Multiplier, and 8×8 Vedic Multiplier circuits, respectively. Numerous parameters like area, clock latency, and quantum cost were calculated using the QCAD tool.

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Section: A Majority Gate Logicmentioning

confidence: 99%

Section: F Proposed Conventional Formula For Nn Vedic Multipliermentioning

confidence: 99%