Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

Abstract

Even the quantum simulation of an apparently simple molecule such as Fe 2 S 2 requires a considerable number of qubits of the order of 10 6 , while more complex molecules such as alanine (C 3 H 7 NO 2 ) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for faulttolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal-oxide-semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal-oxide-semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal-oxide-semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal-oxide-semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal-oxide-semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via timedivision, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm 2 for the 10 and 7-...

Coherent transport of quantum states by deep reinforcement learning

“…In solid-state quantum devices based on either silicon [20] or gallium arsenide [21], the qubit can be encoded, for instance, into spin states of either excess electron(s) or hole(s) in quantum dots [9]. CTAP was originally developed for single-electron states in single-occupied quantum dots, but it can be also extended to more complex spin states, such as for hybrid qubits based on triplets of spin.…”

“…By exploiting such ansatz solution of pulsing the barrier control gates between the dots in a "reversed order" with respect of what intuition would naturally suggest, the process displays truly quantum mechanical behavior, provided that the array consists of an odd number of dots. We already explored separately silicon-based quantum information processing architectures [8,9], including the coherent transport by adiabatic passage of multiple-spin qubits into double quantum dots [10], and heuristic search methods, such as genetic algorithms, to find a universal set of quantum logic gates [11,12], and separately the application of deep reinforcement learning to classical systems [13][14][15]. Here we demonstrate that DRL implemented in a compact neural network can, first of all, autonomously discover the analogue of the counter-intuitive gate pulse sequence without any prior knowledge, therefore finding a control path in a problem whose solution is far from the equilibrium of the initial conditions.…”

Semiconductor quantum computation

“…Now that high fidelity control and readout of single-and two-qubit gates in semiconductor have been demonstrated, the next challenge lies in how to scale it to tens and hundreds of qubits. Corresponding constraints and problems were investigated thoroughly since 2015, including the geometry and operation time constraints [177,178], engineering configuration for quantum-classical interface [179][180][181][182], and even the quantifying of system extensibility [183]. In the light of these discussions, several proposals for scaling up were proposed, varying from the crossbar network [38,39] for spin-1/2 qubits in silicon MOS quantum dots, the two dimensional lattice of donor qubits in silicon [35,36], to the hybrid architecture like donor-dot structure [37] and flip-flop qubit structure [113].…”

Is all-electrical silicon quantum computing feasible in the long term?

“…Another fundamental aspect is related to the realization of devices able to interconnect remote sites composing the quantum circuit to transfer information [67,68]. In order to overcome the problem of interaction between distant qubits, different routes have been pursued: the SWAP chain protocol [4,5] and the coherent tunneling by adiabatic passage (CTAP) scheme [69,70,71]. The SWAP method is based on the sequential repetition of SWAP gates between adjacent qubits.…”

“…Such technology based on quantum dots, being is either Si-MOS or Si/SiGe, requires industrial class fabrication on 300 mm wafers. To achieve such goal, the footprint of the actual qubit which includes the wiring according to the design rules of a technology node has been evaluated [5]. The choice of all-electrical hybrid spin qubits requires spins to be sufficiently close to allow an operation time compatible with fault tolerant quantum computing.…”