Quasi-3D Thermal Model of Stacked IC-TSV-BGA Package

Petrosyants, Konstantin O.; Ryabov, Nikita I.

doi:10.1109/therminic.2019.8923865

Cited by 7 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Previously the correct simplification of the problem for the BGA packages [6], which shortenes the CPU time was proposed.…”

Section: Introductionmentioning

confidence: 99%

Quasi-3D Numerical Thermal Modelling of Electronic Systems in Package

Petrosyants,

Ryabov

2024

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

The technology of three-dimensional (3D) packaging currently provides an increase in the efficiency of various electronic systems, bringing the volume of the package and heat dissipation into proper correlation. For many types of modern 3D packages the electro-thermal properties were not yet investigated. So the thermal modelling of 3D system in package (SiP) constructions became obliged for package designers. The commercial universal fully-3D simulators are not effective for practical engineers because of the complexity in using. The problem-oriented method called “Quasi-3D”was proposed and software tool Quasi-3D-Overheatwas developed to save the pre- and post-processing labour and CPU time. Numerical thermal modelling for different types of modern SiP structures: bridge-chip; p2 Pack; chip stack with TSV; embedded silicon fan-out was carried out and compared with measured temperatures. Simulation error was not more than 10–15%.

show abstract

“…Previously the correct simplification of the problem for the BGA packages [6], which shortenes the CPU time was proposed.…”

Section: Introductionmentioning

confidence: 99%

Quasi-3D Numerical Thermal Modelling of Electronic Systems in Package

Petrosyants,

Ryabov

2024

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

show abstract

“…BGA packaging, a new type of surface mount multi-terminal packaging technology, overcomes the limitation of the number of I/O ports in the peripheral for wire bonding [6,7]. The BGA chip is mounted on the carrier board through solder joints in the form of an array [8][9][10]. This packaging technology not only expands the space of electronic devices but also greatly expands the number of I/O ports [11].…”

Section: Introductionmentioning

confidence: 99%

Survey on Fatigue Life Prediction of BGA Solder Joints

et al. 2022

View full text Add to dashboard Cite

With the development of science and technology, consumers’ requirements for various electronic devices present a trend of more diverse functions and thinner bodies. This makes integrated circuits mounted in electronic products and their packaging more vital to satisfying the above requirements. Ball grid array (BGA) packaging is widely used in the field of microelectronic manufacturing industries due to its multiple I/O volumes and excellent electric characteristics. However, due to environmental loads such as vibration and impact during its production and application, defects inevitably emerge in BGA solder joint defects, which will lead to the failure of electronic products. This article summarizes the state-of-the-art research on the factors, analysis methods, and models for the fatigue failure of BGA chips. After rigorous discussions concerning this research, some theoretical suggestions are provided for BGA packaging in reliability analysis and the establishment of evaluation standards.

show abstract