Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages

Abstract

The problem of thermal modeling of modern three-dimensional (3D) integrated circuit (IC) systems in packages (SiPs) is discussed. An effective quasi-3D (Q3D) approach of thermal design is proposed taking into account the specific character of 3D IC stacked multilayer constructions. The fully-3D heat transfer equation for global multilayer construction is reduced to the set of coupled two-dimensional (2D) equations for separate construction layers. As a result, computational difficulties, processor time, and RAM volume are significantly reduced, while accuracy can be provided. A software tool, Overheat-3D-IC, was developed on the base of the generalized Q3D package numerical model. For the first time, the global 3D thermal performances across the modern integrated circuit/through-silicon via/ball grid array (IC-TSV-BGA) and multi-chip (MC)-embedded printed circuit board (PCB) packages were simulated. A ten times decrease of central processing unit (CPU) time was achieved as compared with the 3D solutions obtained by commercial universal 3D simulators, while saving the sufficient accuracy. The simulation error of maximal temperature TMAX determination for different types of packages was not more than 10–20%.

An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias

“…In the published studies, the maximum error of thermal conductivity in [21] is approximately 15%, and the temperature difference in [17] is below 7.5%. The simulation error of maximal temperature in [28] is less than 20%. The error of the proposed model is within 10% for thermal conductivity, and the maximum temperature error is 5.53%.…”

“…Han et al [27] proposed a thermal resistance network model based on 3D structures, and the proposed model could describe the temperature distribution of 3D structures. Konstantin O et al [28] proposed an equivalent thermal model by using a quasi-3D approach, and the computational difficulties, processor time, and RAM volume were significantly reduced, while the simulation error of the maximal temperature was less than 20%. Wu et al [29] proposed a thermal model using Laplace's equation and the thermal resistance network, which could accurately predict the temperature of a heat source on the chip in these models; however, the 1D network was a simple model, and its accuracy was low.…”

A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging

“…Modeling is a must for finite-element analysis, but the 3D kind of SiP is complicated, and if the simulation’s accuracy is to be ensured, the computational time will undoubtedly grow and the efficiency will be significantly decreased. The global multi-structure 3D model is reduced to a 2D structure with separate structural coupling connections [ 62 ] when a quasi-3D structure is utilized, which can meet the accuracy requirements and speed up FEA computations. In general, FEA methods still address modeling problems, especially concentrating on the cross-scale and cross-dimensional aspects of 3D models.…”

Design and Simulation of a System-in-Package Chip for Combined Navigation

“…The signal path between chips needs to be high-speed and low-noise, while the power plane needs to provide stable voltage and sufficient current. In addition, microsystems need good heat dissipation to avoid performance degradation and failures caused by high temperatures [20][21][22][23]. Temperature causes thermal stress, and temperature mismatch is the main cause of the warping of microsystem structures [24].…”