Quasi-planar bulk CMOS technology for improved SRAM scalability

Shin, Changhwan; Tsai, Chen Hua; Wu, Mei Hsuan; Chang, Chih-Kai; Liu, You Ren; Kao, Chih Yang; Lin, Guan Shyan; Chiu, Kai Ling; Fu, C.; Tsai, Cheng‐Hung; Liang, C. W.; Nikolić, Borivoje; Liu, Tsu‐Jae King

doi:10.1016/j.sse.2011.06.022

Cited by 8 publications

(8 citation statements)

References 11 publications

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“…Besides the performance improvement provided by the n-type transistors, the p-type transistors (i.e., the pull-up (PU) transistors in the SRAM cell) evidently achieve the greatest The PMOS demonstrated a performance enhancement of 4.5×, primarily caused by (i) the narrow layout width of the PU device (i.e., increased stress effects) and (ii) the improved hole mobility for (110) sidewall surfaces of the channel region (note that the electron mobility is degraded for the same surface directions [7]). This data has been adapted from [11] 6.3.2 Suppressed V T Variation by the QPT Structure Figure 6.4 shows the V T variation characteristics of the PG/PD/PU transistors in an SRAM cell. For all the three transistors in the SRAM bit cell, it is observed that the subthreshold slope becomes steeper and thereby V T is lowered because of the increased gate controllability in the QPT bulk MOSFETs.…”

Section: Improved Performance In Qpt Bulk Mosfet (Vs Conventional Momentioning

confidence: 99%

“…a V tsat of NMOS pass-gate (PG), b V tsat of NMOS pull-down (PD), and c V tsat of PMOS pull-up (PU). This data has been adapted from [11] considered as a significant gating issue. Thus, the V T variation can be improved with the removal process of the STI oxide, owing to the advanced electrostatic coupling effect of the quasi-planar device structure.…”

Section: Improved Performance In Qpt Bulk Mosfet (Vs Conventional Momentioning

confidence: 99%

“…Note that the drawn channel width is in the range of 120 nm to 1 µm and the drawn channel length is in the range of 36 nm-0.2 µm. This data has been adapted from [11] …”

Section: Improved Short Channel Effect In the Qpt Bulkmentioning

confidence: 99%

See 2 more Smart Citations

Quasi-Planar Trigate (QPT) Bulk MOSFET

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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Section: Improved Performance In Qpt Bulk Mosfet (Vs Conventional Momentioning

confidence: 99%

Section: Improved Performance In Qpt Bulk Mosfet (Vs Conventional Momentioning

confidence: 99%

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Quasi-Planar Trigate (QPT) Bulk MOSFET

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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“…The LER-induced V TH variation in CMOS devices is mostly dominated by a few short channels (called lucky channels) along the channel width direction, and therefore, the short-channel-effect robust device structures can reduce the LER-induced V TH variation in the given LER profile. For example, multigate devices such as FinFETs and tri-gate MOSFETs [11,12] and ultra-thin-body devices such as FD-SOI MOSFETs [13] are good candidates to overcome the V TH variation by the LER, primarily, because of their improved gate-to-channel capacitive coupling (in comparison with conventional planar bulk MOSFETs).…”

Section: Understanding: Random Variations 1 Line Edge Roughness mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

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“…To surmount the LER-induced V TH variation, a device structure that is strongly immune to short-channel effects should be used. For example, multi-gate devices such as FinFETs and tri-gate MOSFETs [6,7] and ultra-thin-body devices such as Fully Depleted Silicon-On-Insulator (FD-SOI) MOSFETs [8] are good candidates to overcome the LER-induced V TH variation, due primarily to their improved gate-to-channel capacitive coupling (in comparison with conventional planar bulk MOSFETs).…”

Section: Introductionmentioning

confidence: 99%

State-of-the-art silicon device miniaturization technology and its challenges

Shin

2014

IEICE Electron. Express

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Complementary Metal-Oxide-Semiconductor (CMOS) process and silicon device technologies have progressed dramatically in the last 950 years. The achievements of semiconductor industry have dramatically improved the human lifestyle making it smarter. One of the biggest factors in this change is the continued CMOS scaling. However, at sub-30-nm CMOS technology nodes, one of the main technical barriers for reducing the size of CMOS silicon devices is the parametric failure caused by random variations such as line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). This paper discusses these issues in terms of (1) the physical understanding and quantitative evaluation of each random variation source, and (2) the technical solutions to address each of these random variation issues. Lastly, the silicon device scaling scenario from the past, the present and through to the future (i.e., 90 nm technology down to sub-10-nm technology) is briefly discussed.

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Quasi-planar bulk CMOS technology for improved SRAM scalability

Cited by 8 publications

References 11 publications

Quasi-Planar Trigate (QPT) Bulk MOSFET

Quasi-Planar Trigate (QPT) Bulk MOSFET

Analysis of Random Variations and Variation-Robust Advanced Device Structures

State-of-the-art silicon device miniaturization technology and its challenges

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