Qubit-Compatible Substrates With Superconducting Through-Silicon Vias

Abstract

We fabricate and characterize superconducting through-silicon vias and electrodes suitable for superconducting quantum processors. We measure internal quality factors of a million for test resonators excited at single-photon levels, on chips with superconducting vias used to stitch ground planes on the front and back sides of the chips. This resonator performance is on par with the state of the art for siliconbased planar solutions, despite the presence of vias. Via stitching of ground planes is an important enabling technology for increasing the physical size of quantum processor chips, and is a first step toward more complex quantum devices with three-dimensional integration.

Low-loss α-tantalum coplanar waveguide resonators on silicon wafers: fabrication, characterization and surface modification

“…On average, the Q i,low values after the HF treatment obtained in this work are around 2•10 6 . These values are in the range of α-Ta CPW resonators of similar size reported on both Si [46] and sapphire [44,48]. Transmon qubits made of α-Ta with record Q i of 7.1•10 6 and 11.8•10 6 have also been reported by Place et al [32] and Wang et al [33], respectively, while our record Q i,low is 4.5•10 6 .…”

“…While the deposition of α-Ta directly on thermally oxidized Si [42] substrates has been known since the 90s, it is widely recognized that the silicon oxide at the silicon-tantalum interface has a detrimental effect on the performance of superconducting qubits and resonators. To circumvent the issue, α-Ta coplanar-waveguide resonators, which are short loop proxies for superconducting qubits, have been fabricated with the help of seed layers such as Nb [43,44], tantalum nitride (TaN) [45], and titanium nitride (TiN) [46]. Nonetheless, this approach adds to the processing complexity during both the deposition and etching stages of the metallic layers.…”

Noisy intermediate-scale quantum computers

“…), it is nevertheless extremely difficult to route all the control wires from the perimeter (length ) to individual qubits (density ) due to the unmatched scaling law; let alone to avoid crosstalk between wires. In recent years, there have been substantial efforts to exploit the third dimension to relieve this pain with various technologies borrowed from the semiconductor chip packaging, such as flip-chip bonding and throughsilicon vias [331][332][333][334][335][336][337][338]. Aside from expanding the space for wiring, a different approach is to reuse the wire for multiple targets.…”

Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors

“…The latter motivates the active development of 3D integration strategies such as flip-chip [5][6][7] to avoid overcrowding of circuit elements and vertical routing [8][9][10] of input and output lines to circumvent the scaling limitations associated with lateral wirebonding. Through-silicon visas (TSVs) are needed in some vertical routing approaches [11][12][13][14], and especially for suppression of resonance modes arising from the increased size of SQPs and their packaging.…”