Qubit-driven Fault Simulation

Hahanov, Vladimir; Gharibi, Wajeb; Litvinova, Eugenia; Chumachenko, Svetlana

doi:10.1109/latw.2019.8704583

Cited by 17 publications

(20 citation statements)

References 11 publications

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“…In design and test, three main forms of describing processes and phenomena are used: tabular, analytical, graph [1,2], [3,4], [5,6], [7,8]. In this case, the matrix (table) and the vector are two forms of describing models that pass into each other.…”

Section: Literature Overviewmentioning

confidence: 99%

“…In this case, the matrix (table) and the vector are two forms of describing models that pass into each other. The vector is a compact form of the truth table in the form of an ordered sequence of output states, if the input address components are sorted in ascending order [1,3], [5,7], [8]. The matrix, if necessary, expands into a one-dimensional vector for the convenience of parallel data processing in register memory.…”

Section: Literature Overviewmentioning

confidence: 99%

“…Further, the implementation of deductive modeling based on the vector form of the description of redundancy logic of faults transportation [5,6], [7,8] is proposed, which makes it possible to significantly simplify the modeling algorithms to process large-scale digital circuits.…”

Section: Literature Overviewmentioning

confidence: 99%

“…3) Determination of rows-addresses in these columns (6)(7)(8)(9), corresponding to the unit values of the coordinates of the column vector 5 output states.…”

Section: Algorithmmentioning

confidence: 99%

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Developing method of vector synthesis deductive logic forcomputer systems fault analysis

Hahanova¹

2022

HAIT

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The article is devoted to the development of models and methods for fault analysis for examinate test patterns. Deductive fault simulation of digital devices is the most advanced technology that serves the field of design and testing of modern computer systems. At the same time, fault simulation solves the problem of assessing the quality of the test in the class of single constant defects. However, the computational complexity of obtaining deductive formulas, estimated as n3 , is a rather difficult task for high-dimensional RTL-level functional circuits, so the deductive method is usually used only for digital circuits represented at the gate level. Next, we propose a vector method for synthesis deductive formulas for digital schemes represented by RTL elements. This method became possible due to the element description of any complexity in the form of output states vector for combinational device. The model of xor-relationships between the wonderful logical functions (or, xor, and) of digital objects is improved, which is convoluted into zero-space. It makes possible to solve the problems of design and test, machine learning, search for similarities-differences, and destructive components in processes and phenomena. The advantages of the vector model for a compact description of objects, functions and structures are determined. It is proposed to replace analytical expressions that require algorithmically complex calculating, with vector data structures for describing functional logic. Vector-deductive method for synthesis formulas for transporting input fault lists is proposed. It has a quadratic computational complexity of register operations. The coordinate-vector model of defects is considered, not tied to input variables, which can be used for efficient processing of complex logic circuits when assessing the quality of synthesized tests. An algorithm for the synthesis of deductive vectors is presented, which differs from the known ones in the technological parallel processing simplicity of truth tables and makes it possible to create structural and logical conditions for simulating faults in digital projects of the gate, register and system description levels. An efficient method for the synthesis of a deductive truth table according to the rule L=T⊕F is proposed. It differs from the known ones by using vector-coordinate parallel xor-operation. It provides the transportation of faults through a functional element of arbitrary complexity.

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Section: Literature Overviewmentioning

confidence: 99%

Section: Literature Overviewmentioning

confidence: 99%

Section: Literature Overviewmentioning

confidence: 99%

“…3) Determination of rows-addresses in these columns (6)(7)(8)(9), corresponding to the unit values of the coordinates of the column vector 5 output states.…”

Section: Algorithmmentioning

confidence: 99%

See 2 more Smart Citations

Developing method of vector synthesis deductive logic forcomputer systems fault analysis

Hahanova¹

2022

HAIT

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show abstract

“…In this case, the matrix (table) and the vector are two forms for describing models that pass into each other. A vector (binary, multi-valued) is a compact form of a truth table in the form of an ordered sequence of output states, if the input address components are sorted in ascending order [7][8][9][10][11][12][13]. The matrix, if necessary, expands into a one-dimensional vector for the convenience of parallel data processing in register memory.…”

mentioning

confidence: 99%

Vector-deductive Memory-based Transactions for Fault-as-address Simulation

Gharibi¹,

Hahanova²,

Hahanov³

et al. 2023

Èlektron. model.

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The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. Vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expressions of logic, which require algorithmically complex calculators, are replaced by output state vectors of elements and digital circuits, focused on the parallelism of register logical procedures on regular data structures. A vector-deductive method for formula synthesis for propagating input lists (data) of faults is proposed, which has a quadratic computational complexity of register operations. A new matrix of deductive vectors has been synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read-write transaction in memory, elimination of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on technological solving all problems of technical diagnosis. In the work, the transition to vector logic in the organization of computing and the elimination of traditional logic presented in the form of tables and analytical expressions were carried out. The use of read-write transactions on memory in the absence of a command system focuses the new vector-logic computing towards deterministic quantum architectures based on stable subatomic memory particles.

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