Queuing Behavior and Packet Delays in Network Processor Systems

Fu, Jing; Hagsand, Olof; Karlsson, Gunnar

doi:10.1109/mascots.2007.56

Cited by 5 publications

(5 citation statements)

References 15 publications

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“…c) IP Lookup and Packet Processing: Shah and Gupta [24] have proposed two algorithms to manage the ternary content-addressable memory so that the incremental update times of the worst case remain small. Kobayashi et al [25] d) Queing in network processing system: Fu et al [30] have studied about the two important aspects, first is the packet delay and the other one is queuing behavior in a NPsystem. They analyzed and modeled the arrival processes for the packet.…”

Section: Related Workmentioning

confidence: 99%

A Design of Intel’s IXP Meant for Embedded Systems

Jain¹,

Jain²

2019

IJRTE

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Technologies to design an embedded system can be of three types: processor technology, IC technology & design technology. Billions of computing systems are built every year for a variety of purpose. They are built within larger electronic devices. These systems perform a one particular function on regular basis. These systems do not recognized by the device's user. These systems are known as embedded system. Broad categories for system implementation are: Application Specific Integrated Circuit, Field Programmable Gate Array, Co-Processor, Application Specific Instruction Processor and General Purpose Processor. From the network processor's designing point of view, it is very important to understand the preliminary characteristics of network applications which are generally based on address lookup, pattern matching, and queuing management which is further classified as Control plane and Data Plane processing. Keywords: Network Processor, General Purpose processor, Field programmable gate array.I.

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Section: Related Workmentioning

confidence: 99%

A Design of Intel’s IXP Meant for Embedded Systems

Jain¹,

Jain²

2019

IJRTE

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“…More attention has been paid to the queue system, where we implement a queuing module that adds random delay to each packet transition time in order to match the proposed distribution with satisfactory results. Here we benefit from latency measurements taken from real routers found in [14,15] as well as [16], showing that packet delays across a router can be approximated with a Weibull distribution. Memory options include multiple DDR and DDR2 SDRAM memory models as well as SRAM memory all of which can be connected either to the system bus or directly to the buffer manager.…”

Section: Modeling Approachmentioning

confidence: 99%

Improving memory subsystem performance in network processors with smart packet segmentation

Karras¹,

Llorente²,

Wild³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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Network processing requirements are climbing at an impressive rate. The introduction of state-of-the-art, high-speed optical links puts additional strain on all electronic components of a network processor. This is particularly true for the memory subsystem, since the traditional performance gap between memory and processor is also present there. A major contribution to improve the performance of the memory subsystem is to define an optimized algorithm for segmenting network packets. The goal is to ensure a minimum number of segments, so as to achieve maximum packet throughput, while maintaining a high level of memory efficiency. In this paper we present two different algorithms, both of which utilize a variable number of segments from different sizes and evaluate them using a variety of stimuli and system configurations in order to determine how different architectural choices impact the performance of the algorithms and the system in general. The results verify that multiple segment size segmentation provides very high storing efficiency with a low number of segments per packet, thus allowing for significantly higher system throughput in comparison with currently used algorithms.

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“…Traditional generalpurpose processors cannot meet such requirements because of their limited processing ability, and poor programmability and scalability. The goals are to provide the performance of traditional ASIC (application-specific integrated circuit) processors and the programmability of general-purpose processors [8]. The network processor is designed and optimized specially for network packet processing [7], which is an important component for computational processes in Internet-based applications.…”

Section: Introductionmentioning

confidence: 99%

“…The network processor is designed and optimized specially for network packet processing , which is an important component for computational processes in Internet‐based applications. The goals are to provide the performance of traditional ASIC (application‐specific integrated circuit) processors and the programmability of general‐purpose processors .…”

Section: Introductionmentioning

confidence: 99%

A profiling based task scheduling approach for multicore network processors

Tang

You

Tang

et al. 2012

Concurrency and Computation

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Multicore network processors have been playing an increasingly important role in computational processes, which emphasize on scalability and parallelism of the systems, in distributed environments especially in Internet-based delay-sensitive applications. It is an important but unsolved issue, however, to efficiently schedule tasks in network processors with multicore and multithread for improving the system throughput as much as possible. Profiling can gather runtime environment information and guide the compiler to optimize programs through scheduling tasks based on the runtime context. This paper proposes a profiling-based task scheduling approach, targeting on improving the throughput of multicore network processor (Intel IXP) systems in the balanced pipeline way. In this work, we investigate a profiling-based task scheduling framework, a task scheduling algorithm, and a set of performance models. Our task allocation scheme maps tasks onto the pipeline architecture and multiple threads of network processors in parallel, which incorporates the profiling context and global thread refinement. We evaluate our task scheduling algorithm by implementing representative network applications on the Intel IXP network processor. Experimental results demonstrate that our algorithm is able to schedule tasks in a balanced pipeline fashion and achieve the high throughput and data transmission rate.

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Queuing Behavior and Packet Delays in Network Processor Systems

Cited by 5 publications

References 15 publications

A Design of Intel’s IXP Meant for Embedded Systems

A Design of Intel’s IXP Meant for Embedded Systems

Improving memory subsystem performance in network processors with smart packet segmentation

A profiling based task scheduling approach for multicore network processors

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