The precision physics needs at TeV-scale linear electron-positron colliders (ILC and CLIC) require a vertex-detector system with excellent flavour-tagging capabilities through a measurement of displaced vertices. This is essential, for example, for an explicit measurement of the Higgs decays to pairs of b-quarks, c-quarks and gluons. Efficient identification of top quarks in the decay t → W b will give access to the ttH-coupling measurement. In addition to those requirements driven by physics arguments, the CLIC bunch structure calls for hit timing at the few-ns level. As a result, the CLIC vertex-detector system needs to have excellent spatial resolution, full geometrical coverage extending to low polar angles, extremely low material budget, low occupancy facilitated by time-tagging, and sufficient heat removal from sensors and readout. These considerations challenge current technological limits. A detector concept based on hybrid pixel-detector technology is under development for the CLIC vertex detector. It comprises fast, low-power and small-pitch readout ASICs implemented in 65 nm CMOS technology (CLICpix) coupled to ultra-thin planar or active HV-CMOS sensors via low-mass interconnects. The power dissipation of the readout chips is reduced by means of power pulsing, allowing for a cooling system based on forced gas flow. This contribution reviews the requirements and design optimisation for the CLIC vertex detector and gives an overview of recent R&D achievements in the domains of sensors, readout and detector integration.