Race analysis of digital systems without logic simulation

Harrison, R. A.; Olson, Daniel J.

doi:10.1145/800158.805063

Cited by 5 publications

(1 citation statement)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There have been a number of previous approaches to the verification of" timing constraints in digital systems; these can be grouped into two main categories: logic simulation [3,4,5,10] and worst-case path analysis [2,12].…”

Section: P R E V I O U S a P P R O A C H E Smentioning

confidence: 99%

Verification of timing constraints on large digital systems

McWilliams¹

1980

Proceedings of the Seventeenth Design Automation Conference on Design Automation - DAC '80

View full text Add to dashboard Cite

A new approach to the verification of the timing constraints on large digital systems has been developed.The associated algorithm is computationally very efficient, and provides early and continuous feedback about the timing aspects of synchronous sequential circuits as they are designed. It also provides means for conveniently verifying the design in sections, permitting the section-by-section timing verification of designs which are too large to examine as a unit on existing computer systems. A system using this algorithm has been implemented, and has been used to verify the timing constraints on the design of the S-I Mark IIA processor. I N T R O D U C T I O NIn order that a digital system perform correctly, a designer must take into account the possible propagation delays associated with each of the elements making up the system. If a path through a digital system has either too long or too short a delay associated with it, then the value of the circuit may be wrong at a critical point, causing the circuit to calculate an incorrect result. This is called a timing error.Digital logic as it is currently implemented is intrinsically susceptible to such errors, and their complete elimination from all portions of a digital logic system is essential to a realistic guarantee that the logic will perform reliably and reproducibly under all variations in data and programs. This paper addresses the early and efficient detection of these timing errors, so that digital logic designers can henceforth frequently examine their designs for them as the design proceeds, thereby finding timing errors before the design progresses so far that the errors become difficult to eliminatd.A system which uses these ideas has been implemented and is called the SCALD Timing Verifier. It inputs the design of a sjmchronous sequential system given in the SCALD Hardware Description Language [6], and analyzes it, comprehensively searching it for timing errors. SCALD (Structured Computer-Aided Logic Design) is a complete computer-aided design system which inputs a graphics-based, hierarchical description of a digital logic design, and thereupon generates a complete set of low-level documentation which includes that necessary to implement it in hardware [8,7]. The Timing Verifier performs a complete timing constraint verification based on the minimum and maximum propagation delays of the circuit components, their set-up and hold times, minimum pulse width constraints, and wire delays.One of" the principal features of the Timing Verifier is its ability to verify designs by modules. This not only permits its use on computers with limited memory size, but also allows timing constraints to be checked as a design progresses, even on a day-by-day basis. This is particularly important in that it allows timing errors to be corrected before they have a chance to propagate their effects throughout the design, or to cause major changes to be required late in the design. It also supports an accurate estimation of the cycle time of a digital logic machine bef...

show abstract

Section: P R E V I O U S a P P R O A C H E Smentioning

confidence: 99%

Verification of timing constraints on large digital systems

McWilliams¹

1980

Proceedings of the Seventeenth Design Automation Conference on Design Automation - DAC '80

View full text Add to dashboard Cite

show abstract

Computer aids for VLSI design

1987

Microprocessors and Microsystems

View full text Add to dashboard Cite

Developments in Logic Network Path Delay Analysis

Bening¹,

Lane²,

Alexander³

et al. 1982

19th Design Automation Conference

View full text Add to dashboard Cite

This paper discusses path delay analysis programs as an alternative to detailed logic simulation for finding timing problems in logic networks. Fundamentals of path delay analysis are reviewed, and several previously reported methods are surveyed. This is followed by a more detailed description of a delay analysis program that we have recent]y implemented. Our implementation uncovers a wide variety of timing problems and has a run time that is linearly proportional to the number of gates in the network. Other principle features are that timing information loss is minimized by treating 0-to-1 and 1-to-0 delays separately, and the user is given the capability of selectively disabling paths in order to discover timing problems that would otherwise remain hidden.19th Design Automation Conference 0420-0098/82/0000/0605500.75 © 1982 IEEE Paper 35.1

show abstract

Race analysis of digital systems without logic simulation

Cited by 5 publications

References 7 publications

Verification of timing constraints on large digital systems

Verification of timing constraints on large digital systems

Computer aids for VLSI design

Developments in Logic Network Path Delay Analysis

Contact Info

Product

Resources

About