RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation

Azad, Zahra; Yang, Guowei; Agrawal, Rashmi; Petrisko, Daniel; Taylor, Michael; Joshi, Ajay

doi:10.1145/3531437.3539725

Cited by 7 publications

(5 citation statements)

References 10 publications

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“…• RACE [42]: In the RACE SoC, the hardware accelerator executes the en/decryption operation, while the remaining operations (error sampling and en/decoding) are performed on the BP processor. We modified SEAL-Embedded library to invoke calls to en/decryption operations on the accelerator.…”

Section: Evaluation a Methodologymentioning

confidence: 99%

“…1) Memory Bank Organization for Parallel NTT: Moving to a multi-port memory bank design is not an efficient solution as increasing the number of ports will quadratically increase the memory area overhead [42]. To reduce the memory area overhead, we still use the 1RW memory banks but we linearly increase the number of memory banks as we increase the number of BFUs.…”

Section: Further Optimizations To Nttmentioning

confidence: 99%

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RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

Azad¹,

Yang²,

Agrawal³

et al. 2023

Preprint

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Today edge devices commonly connect to the cloud to use its storage and compute capabilities. This leads to security and privacy concerns about user data. Homomorphic Encryption (HE) is a promising solution to address the data privacy problem as it allows arbitrarily complex computations on encrypted data without ever needing to decrypt it. While there has been a lot of work on accelerating HE computations in the cloud, little attention has been paid to the message-to-ciphertext and ciphertext-to-message conversion operations on the edge. In this work, we profile the edge-side conversion operations, and our analysis shows that during conversion error sampling, encryption, and decryption operations are the bottlenecks. To overcome these bottlenecks, we present RISE, an area and energy-efficient RISC-V SoC. RISE leverages an efficient and lightweight pseudorandom number generator core and combines it with fast sampling techniques to accelerate the error sampling operations. To accelerate the encryption and decryption operations, RISE uses scalable, data-level parallelism to implement the number theoretic transform operation, the main bottleneck within the encryption and decryption operations. In addition, RISE saves area by implementing a unified en/decryption datapath, and efficiently exploits techniques like memory reuse and data reordering to utilize a minimal amount of on-chip memory. We evaluate RISE using a complete RTL design containing a RISC-V processor interfaced with our accelerator. Our analysis reveals that for message-to-ciphertext conversion and ciphertextto-message conversion, using RISE leads up to 6191.19× and 2481.44× more energy-efficient solution, respectively, than when using just the RISC-V processor.

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Section: Evaluation a Methodologymentioning

confidence: 99%

Section: Further Optimizations To Nttmentioning

confidence: 99%

RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

Azad¹,

Yang²,

Agrawal³

et al. 2023

Preprint

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show abstract

“…Hagen et al presented CHOCO, a client-optimized system for encrypted offload processing that supports both B/FV and CKKS HE schemes, in 2022 [7]. Recently, Azad et al proposed RACE, a custom-designed, area-and energy-efficient RISC-V SoC for the data ENC-DEC using CKKS HE, in 2022 [8]. RACE unified the ENC-DEC data path and effectively utilized memory reuse and data reordering to conserve on-chip resources.…”

Section: Related Workmentioning

confidence: 99%

Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption

Lee,

Duong,

Lee

2023

Sensors

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With the increasing number of edge devices connecting to the cloud for storage and analysis, concerns about security and data privacy have become more prominent. Homomorphic encryption (HE) provides a promising solution by not only preserving data privacy but also enabling meaningful computations on encrypted data; while considerable efforts have been devoted to accelerating expensive homomorphic evaluation in the cloud, little attention has been paid to optimizing encryption and decryption (ENC-DEC) operations on the edge. In this paper, we propose efficient hardware architectures for CKKS-based ENC-DEC accelerators to facilitate computations on the client side. The proposed architectures are configurable to support a wide range of polynomial sizes with multiplicative depths (up to 30 levels) at a 128-bit security guarantee. We evaluate the hardware designs on the Xilinx XCU250 FPGA platform and achieve an average encryption time 23.7× faster than that of the well-known SEAL HE library. By reducing time complexity and improving the hardware utilization of cryptographic algorithms, our configurable CKKS-supported ENC-DEC hardware designs have the potential to greatly accelerate cryptographic processes on the client side in the post-quantum era.

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“…Chen et al [18] improve the NTT in their processor, taking advantage of dual memory access. The integration of NTT across different platforms to support the new PQC is evolving [19]- [22].…”

Section: Introductionmentioning

confidence: 99%

Efficient number theoretic transform accelerator for CRYSTALS-Kyber

Nguyen,

Anh Pham,

Nguyen

et al. 2024

IJEECS

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<p>The national institute of standards and technology (NIST) has presented its draft of the module-lattice-based key-encapsulation mechanism standard (MLBKEMS), choosing cryptographic suite for algebraic lattices (CRYSTALS)- Kyber as the base encryption. Existing hardware implementations of modern cryptography will need to process the new standard efficiently. The primary process in CRYSTALS-Kyber key-encapsulation mechanism (KEM) is the number theoretic transform (NTT), which requires heavy computing power. This paper contributes an efficient hardware accelerator for NTT and inverse NTT (INTT) by CRYSTAL-Kyber parameters. The proposed design utilizes the K-RED algorithm for reducing polynomial multiplication. It also incorporates the BrentKung method for efficient modular addition and subtraction operation with an address generator to control the sequences of computation. On the Xilinx Artix 7 field programmable gate array (FPGA), our design achieves 262 MHz clock speed, utilizing only 1405 LUTs.</p>

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RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation

Cited by 7 publications

References 10 publications

RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption

Efficient number theoretic transform accelerator for CRYSTALS-Kyber

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