2021
DOI: 10.46586/tches.v2022.i1.557-588
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Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware

Abstract: BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, in which performance plays a significant role in the third round. This paper presents FPGA implementations of BIKE with the best area-time performance reported in literature. We optimize two key arithmetic operations, which are the sparse polynomial multiplication and the polynomial inversion. Our sparse multiplier achieves time-constancy for sparse polynomials of indefinite Hamming weight used in BI… Show more

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Cited by 14 publications
(3 citation statements)
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“…In addition, the computation of 10r inner products during the decoding procedure results in a decapsulation that runs 6 to 9 times slower than that of HQC. Several hardware benchmarks also confirm that performance of BIKE would be suitable for most applications [191][192][193][194].…”
Section: Bike (Bit Flipping Key Encapsulationmentioning
confidence: 69%
“…In addition, the computation of 10r inner products during the decoding procedure results in a decapsulation that runs 6 to 9 times slower than that of HQC. Several hardware benchmarks also confirm that performance of BIKE would be suitable for most applications [191][192][193][194].…”
Section: Bike (Bit Flipping Key Encapsulationmentioning
confidence: 69%
“…In addition, the computation of 10r inner products during the decoding procedure results in a decapsulation that runs 6 to 9 times slower than that of HQC. Several hardware benchmarks also confirm that performance of BIKE would be suitable for most applications [189][190][191][192].…”
Section: Bike (Bit Flipping Key Encapsulationmentioning
confidence: 69%
“…The complexity of PQC solutions makes it paramount to optimize their execution to guarantee proper performance even on embedded devices at the edge [3]- [5]. The literature provides the official x86-64 software implementations of BIKE [1], constant-time versions [6], and works targeting other architectures [7], [8], while state-of-the-art hardware implementations include the official FPGA-based one [9], that instantiates the whole KEM in a unified accelerator, and an This work was supported by the European Commission and the Italian Ministry of Enterprises and Made in Italy (MIMIT) under the KDT JU "ISOLDE" project (Grant No. 101112274).…”
Section: Introductionmentioning
confidence: 99%