Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

Abstract

In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall Effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid CMOS/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-basedlook-up table for ultralow power and highly reliable FPGA designs

“…It is generally composed of three components: 1) a sense amplifier (SA) to read a selected MTJ cell in the STT-LUT and produce full swing output voltage; 2) a selection tree with volatile logic data to choose a unique MTJ cell; 3) a write circuit to program the input data in a selected MTJ cell. In this design, the MTJ cells are directly connected to the selection tree circuit and the sense amplifier is shared among them [15][16][17][18][19][20][21].…”

“…However, the critical issues in SRAM-based FPGA devices are the increasing leakage currents in the configuration memory and vulnerability against particle strikes. The integration of STTRAM in FPGA instead of SRAM is one of the most promising solutions to overcome these issues [15][16][17][18][19][20][21][22][23]. Spin-torque transfer random access memory (STTRAM) is a promising memory technology for high-density on-chip caches due to its low leakage power and robustness against particle strikes.…”

Clockless Spin-based Look-Up Tables with Wide Read Margin

“…Innovations using emerging devices within FPGAs have been sought to bridge the gaps needed to overcome the limitations of SRAM-based FPGAs. High-endurance non-volatile spin-based LUTs have been studied in the literature as promising alternatives to SRAM-based LUTs, Flash-based LUTs, and other state-of-the-art emerging LUTs such as resistive random access memory (RRAM)based LUTs and phase change memory (PCM)-based LUTs [2,4,[10][11][12]14]. Spin-based devices offer non-volatility, near-zero static power, high endurance, and high integration density [9,13].…”

“…Spin-based devices offer non-volatility, near-zero static power, high endurance, and high integration density [9,13]. The spin-based LUTs presented in the literature [2,4,[10][11][12]14] require separate read and write operations as well as a clock, which makes these LUTs a suitable candidate for sequential logic operations. However, the main challenge that has not been addressed in the literature is providing a spin-based LUT design for combinational logic operation without the need for a clock.…”

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks

“…Technology heterogeneity recognizes the cooperating advantages of CMOS devices for their rapid switching capabilities, while simultaneously embracing emerging devices for their non-volatility, near-zero standby power, high integration density, and radiation-hardness. For instance, spintronicbased LUTs are proposed in [8], [9], [10] as the primary building blocks in reconfigurable fabrics realizing significant area and energy consumption savings. In this paper, we extend the transition toward heterogeneity along various logic paradigms by proposing a heterogeneous technology fabric realizing both probabilistic and deterministic computational models.…”