Radiation hardened pulsed-latches in 65-nm CMOS

Shah, Jaspal Singh; Sachdev, Manoj

doi:10.1109/ccece.2016.7726599

Cited by 1 publication

(4 citation statements)

References 14 publications

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“…Moreover, at 100% data switching activity, the TSPCER FF consumes 31% and 24% lower power than the TSPC DICE and SCCER FF, respectively. The proposed TSPCER FF consumes 71% to 88% lower power than the recently reported PGDICE [28] FF at 100% to 12.5% data activity. At all data activity, the proposed TSPCER FF consumes less power than the other proposed FFs, makes it more suitable for low-power operation.…”

Section: Flip-flops Power Consumptionmentioning

confidence: 76%

“…A C-element based SEU hardened dual data rate FF [7], a TSPC-DICE FF, and a delay filtered DICE FF [22] can efficiently serve this purpose; however, they suffer from significant t C−Q delay and area overhead. Another previously developed pulsed-gated DICE (PGDICE) uses extra transistors to improve the double node upset; however, it consumes significant extra area and power [28]. Similar to a master-slave D FF, a Quatro-based SEU-hardened FF (MSQuatro) has low delay; however, it suffers from large area overhead [20].…”

Section: Overview Of Existing Seu-hardened Flip-flopsmentioning

confidence: 99%

“…We have designed and laid out the proposed CPQ, C 2 -DICE, TSPCER FFs along with a traditional master-slave D (MSD) FF, a master-slave DICE (MS-DICE) FF without preset and clear [32], a PDICE FF [19], a TSPC-DICE FF [15], a PGDICE [28], a MSQuatro [20], and a SCCER FF [21] in a commercial 65nm CMOS technology. The performance of the FFs is extracted using post-layout simulation considering a wide frequency band from 1 GHz to 5 GHz and a supply voltage of 1 V.…”

Section: Simulation Setupmentioning

confidence: 99%

“…The importance of designing low-power and high-performance timing elements has led to the design of different kinds of low-power latches and FFs in the literature [8,21,30,19,15,32,7,22,29,28,11,20]. A number of papers have proposed new styles of latches and FFs that improve power, speed, and energy or demonstrate special characteristics of timing and soft error robustness.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

Islam

2018

J Electron Test

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An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and larger die sizes. The technology scaling followed Moore's law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flipflops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C 2 -DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Postlayout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1-5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.

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Section: Flip-flops Power Consumptionmentioning

confidence: 76%