Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach

Yang, Jianlei; Wang, Peiyuan; Zhang, Yaojun; Cheng, Yuanqing; Zhao, Weisheng; Chen, Yiran; Li, Hai

doi:10.1109/tcad.2015.2474366

Cited by 37 publications

(21 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The read circuit consists of a two-branch sensing circuit with equalizing transistors [38] and a voltage sense amplifier with dynamic latched comparator [39] for digital output. Both branches of read circuit are composed by a load pMOS, a read enable nMOS and a clamped nMOS [40] [41]. The read operation is enabled by setting Read En.…”

Section: Spintronic Device Based Energy Efficient Sbgmentioning

confidence: 99%

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

Jia

Yang

Dai

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computingintensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this work, a spintronics based stochastic computing approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build stochastic bitstream generator (SBG) for stochastic computing with hybrid CMOS/MTJ circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and stochastic computing logic. A deviceto-architecture level framework is proposed to evaluate the performance of spintronics based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about 12× than MTJ-based approach with 45% design area overhead and about 26× than FPGA-based approach.

show abstract

Section: Spintronic Device Based Energy Efficient Sbgmentioning

confidence: 99%

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

Jia

Yang

Dai

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…15. The Comparison among Plain MLD [6], the Method Proposed by Jayarani et al [3], and the Proposed Method for Error Detection. Fig.…”

Section: B Experimental Resultsmentioning

confidence: 99%

“…In particular, soft errors are a matter of great concern when planning high accessibility systems or systems utilized as a part of electronic-antagonistic situations [1]- [4]. In memory applications, soft error can change an instruction or any data value [3]- [5]. Almost all system chips have embedded memories like ROM, DRAM, SRAM, flash memory etc.…”

Section: Introductionmentioning

confidence: 99%

Soft Error Tolerance in Memory Applications

Rahman¹,

Sultana²,

Uddin³

et al. 2018

ijacsa

View full text Add to dashboard Cite

Abstract-This paper proposes a new method to detect and correct multi bit errors in memory applications using a combination of a clustering approach, Bit-Per-Byte error detection technique, and Majority Logic Decodable (MLD) codes. The likelihood of soft errors accelerates with system complexity, reduction in operational voltages, exponential growth in transistor per chip, increases in clock frequencies, breakdown of memory reliability and device shrinking. Memories are the sensitive part of a computer system. Soft errors in memories may cause an instruction to malfunction. Several techniques are already in practice to mitigate the soft errors. Majority logic decodable codes are proved as effective for memory applications because of their ability to correct a massive number of errors. Since memories are used to hold large number of bits that's the restraint of Majority logic decodable codes method, so we emphasize on the size of data word in this method. The proposed method aims to detect and correct up to seven bit errors with lesser computational time. It works in an efficient manner in case of adjacent errors which is not possible in Majority logic decodable codes (MLD). It is delineated by Experimental reviews that the proposed approach outperforms existing dominant approach with respect to number of erroneous bit detection and correction, and computational time overhead.

show abstract

“…While the most of released charges are absorbed in the struck junction, the remained charges are diffused into the substrate. In particular, if these impinging charges are collected by a sensitive node such as the reverse biased drain pn junction of the access transistor in an eDRAM cell while it is on the off state, it probably changes the amount of the potential at the drain node and results in the flip of the initial state [11] [20]. The Radiation-induced Soft Error Rate (SER) can be expressed as:…”

Section: Single Event Effectmentioning

confidence: 99%

Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis

Khoshavi

Chen

Wang

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

Whereas contemporary Last Level Cache (LLC) designs occupy a significant fraction of total die area in chipmultiprocessors (CMPs), approaches to deal with the vulnerability increase of LLC against Single Event Upset (SEU) and Multi-Bit Upsets (MBUs) are sought. In this paper, we focus on reliability assessment of eDRAM LLC to propose a more accurate and application-relevant vulnerability estimation approach compared to conventional LLC SEU analysis methods. In particular, the eDRAM Bit Upset Vulnerability Factor (BUVF) is proposed and an algorithm is developed to assess its behavior for soft errors using experimental benchmark suites. BUVF explicitly targets the vulnerable portion of the eDRAM refresh cycle where the critical charge varies depending on write voltage, storage and bit-line capacitance. Results for the PARSEC benchmark suite indicated that vulnerable sequences account for about 27.2% of data array lifetime in the cache, among which the Read-Read (RR) access sequence contributes about 23.4%. Furthermore, regardless of the size of the vulnerable data set located in an RR sequence over a short interval, the corresponding region of cache is seen to contribute negligible vulnerability to BUVF, which results from spending a small fraction of program execution time undergoing RR sequences. We recast the problem of reliable eDRAM LLC design as a straightforward search for reduced BUVF.

show abstract

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach

Cited by 37 publications

References 28 publications

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

Soft Error Tolerance in Memory Applications

Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis

Contact Info

Product

Resources

About