Radix-2n serial–serial multipliers

Abstract

All serial-serial multiplication structures reported in the literature has been confined to bit serial-serial multipliers. In this paper, an architecture for digit serial-serial multipliers is presented. A set of designs are derived from the radix-2 n design procedure which was first reported by the authors for the design of bit level pipelined digit serial-parallel structures [8].One significant aspect of the new designs is that they can be pipelined to the bit level and give the designer the flexibility to obtain the best trade off between throughput rate and hardware cost by varying the digit size and the number of pipelining levels. Also in this paper an area efficient digit serial-serial multiplier is proposed which provides a 50% reduction in hardware without degrading the speed performance. This is achieved by exploiting the fact that some cells are idle for most of the multiplication operation. In the new design, the computations of these cells are re-mapped to other cells, which make them redundant. The new designs have been implemented on the S40BG256 device from the SPARTAN family to prove functionality and assess performance. 3 1.

Area-Efficient Digit Serial–serial Two's Complement Multiplier

“…4 Aggoun 4 proposed two implementations: the¯rst uses a basic-block per digit of the operand and the second uses only half the count of basic-blocks and bu®ers the most signi¯cant operands' halves and reroutes them for processing after the least signi¯cant halves are processed. The second implementation is the one we compare with since it occupies less area.…”

“…Lower values of d are in the favor of Aggoun. 4 Taking into consideration circuit elements other than the compressors tree, Aggoun 4 possess extra latency for input bu®ers and input multiplexers. As shown in Table 1, the proposed multiplier is lower in latency for d values of n/2 and n/4.…”

“…On the other hand, unfolding starts with a bit serialserial multiplier and replicates it a number of times equal to the digit width. Other design approaches are based on radix 2 n arithmetic 4,5,8 and ad hoc designs. 1 In this paper, the proposed multiplier adopts the folding approach starting from a fully parallel multiplier and truncating it down to a digit serial-serial multiplier.…”

“…Perhaps one of the¯rst trials to achieve digit serial-serial multipliers was proposed by Aggoun et al 4 They proposed a design that is based on radix-2 n arithmetic and supports bit-levelpipelining. This is achieved by using 4-to-2 compressors 4 instead of adders (A compressor is a unit that reduces four operands to be added to only two).…”

“…However, their proposed multiplier imposes the same constraints as in Ref. 4, in addition to not supporting bit-level-pipelining and introduction of extra startup cycles. That is, the generated digits are not produced immediately starting from the¯rst cycle as in Aggoun 4 or the multiplier proposed in this paper.…”