RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits

Bhattacharya, Koustav; Ranganathan, N.

doi:10.1109/vlsi.design.2009.76

Cited by 11 publications

(5 citation statements)

References 17 publications

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“…Third, the SDC proneness ) (SDC P of each instruction is obtained through the equation (1) ) ( ) ( I D N N SDC P fault SDC × = (1) where SDC N is the SDC count caused by instruction I , fault N is the total number of initial faults attributed to the instruction I , D(I) is the dynamic count ratio of the instruction I .…”

Section: Fault Injection and Training Data Generationmentioning

confidence: 99%

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Identifying SDC-Causing Instructions Based on Random Forests Algorithm

2019

KSII TIIS

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Silent Data Corruptions (SDCs) is a serious reliability issue in many domains of computer system. The identification and protection of the program instructions that cause SDCs is one of the research hotspots in computer reliability field at present. A lot of solutions have already been proposed to solve this problem. However, many of them are hard to be applied widely due to time-consuming and expensive costs. This paper proposes an intelligent approach named SDCPredictor to identify the instructions that cause SDCs. SDCPredictor identifies SDC-causing Instructions depending on analyzing the static and dynamic features of instructions rather than fault injections. The experimental results demonstrate that SDCPredictor is highly accurate in predicting the SDCs proneness. It can achieve higher fault coverage than previous similar techniques in a moderate time cost.

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Section: Fault Injection and Training Data Generationmentioning

confidence: 99%

“…With the processor design trends towards smaller transistor size, lower core voltage and higher frequency, the threat of soft errors becomes more and more serious. [1]. Soft errors could lead to silent data corruption (SDC) which are difficult to be detected.…”

Section: Introductionmentioning

confidence: 99%

Identifying SDC-Causing Instructions Based on Random Forests Algorithm

2019

KSII TIIS

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“…SEU-induced soft errors have been known as one of the major threats to functionality and reliability of space-borne computers and their host spacecrafts. Soft errors may be explicit bit flips in latches or memories, or glitches in combinational logics that can propagate and be captured in latches [9]. If not handled properly, such errors can cause illegal accesses to peripherals, memory overflow, data corruption, false and sometimes fatal data or action outputs, and so on.…”

Section: Introductionmentioning

confidence: 99%

Control Flow Checking at Virtual Edges

2016

KSII TIIS

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Dynamically checking the integrity of software at run-time is always a hot and difficult spot for trusted computing. Control-flow integrity is a basic and important safety property of software integrity. Many classic and emerging security attacks who introduce illegal control-flow to applications can cause unpredictable behaviors of computer-based systems. In this paper, we present a software-based approach to checking violation of control flow integrity at run-time. This paper proposes a high-performance and low-overhead software control flow checking solution, control flow checking at virtual edges (CFCVE). CFCVE assigns a unique signature to each basic block and then inserts a virtual vertex into each edge at compile time. This together with insertion of signature updating instructions and checking instructions into corresponding vertexes and virtual vertexes. Control flow faults can be detected by comparing the run-time signature with the saved one at compile time. Our experimental results show that CFCVE incurs only 10.61% performance overhead on average for several C benchmark programs and the average undetected error rate is only 9.29%. Compared with previous techniques, CFCVE has the characteristics of both high fault coverage and low memory and performance overhead.

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“…Single Error Correction Double Error Detection (SECDED) scheme is normally used for ECC due to its simple architecture, but Double Error Correction (DEC) can be implemented using more logics and gates and increases power. Also circuit sizing methods were also proposed [2]. Circuit level techniques can increase the soft error immunity using hardened memory cells.…”

Section: Introductionmentioning

confidence: 99%

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

Kim

Guthaus

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Electric devices should be resilient because reliability issues are increasingly problematic as technology scales down and the supply voltage is lowered. Specifically, the Soft-Error Rate (SER) increases due to the reduced feature size and the reduced charge. This paper describes an adaptive method to lower memory power using a dual V dd in a column-based V dd memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.

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RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits

Cited by 11 publications

References 17 publications

Identifying SDC-Causing Instructions Based on Random Forests Algorithm

Identifying SDC-Causing Instructions Based on Random Forests Algorithm

Control Flow Checking at Virtual Edges

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

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