RAFT: A router architecture with frequency tuning for on-chip networks

Mishra, Asit K.; Yanamandra, Aditya; Das, Reetuparna; Eachempati, Soumya; Iyer, Ravi; Narayanan, Vijaykrishnan; Das, Chita R.

doi:10.1016/j.jpdc.2010.09.005

Cited by 25 publications

(24 citation statements)

References 27 publications

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“…Moreover, since the contention is variable and highly depending on traffic, a methodology with run-time tuning is preferred to optimize the power consumption with acceptable impacts on performance. In this context, frequency scaling represents one of the most used actuators to achieve such a goal [24].…”

Section: Motivational Examplementioning

confidence: 99%

“…Such a policy outperforms threshold-based ones taken from [24]. Moreover, the scheme can be possibly tuned at high-level: the OS can choose if the policy to run should be more power-oriented or performance-oriented while guaranteeing non saturation of the frequency control.…”

Section: Novel Contributionsmentioning

confidence: 99%

“…Accurate analytical formulation for both the NoC traffic and control policies -The whole methodology focuses on both a controller design and an analytical model that binds the impact of the router frequency on its contention, i.e. the filling level of router buffers, that we use as a proxy for performance [24]. While the model of the process takes steps from [40] it has been greatly improved as described in Section 3.1.…”

Section: Novel Contributionsmentioning

confidence: 99%

“…Mishra et al [24] discussed a fine-grained frequency tuning scheme for NoC routers to optimally manage the power-performance trade-off. In particular the methodology exploits signaling between routers to collect critical information to steer frequency.…”

Section: Noc-based Power-performance Optimizationsmentioning

confidence: 99%

“…Our proposal has been validated against threshold-based policies as the ones proposed in [24]. Moreover, we provide a framework to develop power-performance policies exploiting Dynamic Frequency Scaling actuators, carefully modeled to consider timing and energy overheads, that automatically set the router frequencies according to the actual load.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

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a b s t r a c tNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi-and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ⁄ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting.

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Section: Motivational Examplementioning

confidence: 99%

Section: Novel Contributionsmentioning

confidence: 99%

Section: Novel Contributionsmentioning

confidence: 99%

Section: Noc-based Power-performance Optimizationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A control-based methodology for power-performance optimization in NoCs exploiting DVFS

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2015

Journal of Systems Architecture

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An energy-efficient multi-level RF-interconnect for global network-on-chip communication

Jalalifar

Byun

2019

Analog Integr Circ Sig Process

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A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

Zoni

Terraneo

Fornaciari

2015

J Sign Process Syst

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Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong influence on the performance of the whole chip. On-chip network affects also the overall power consumption, thus requiring accurate early-stage estimation and optimization methodologies. In this scenario, the Dynamic Voltage Frequency Scaling (DVFS) technique have been proposed both for CPUs and NoCs. The promise is to be a flexible and scalable way to jointly optimize power-performance, addressing both static and dynamic power sources. Being simulation a de-facto prime solution to explore novel multi-core architectures, a reliable full system analysis requires to integrate in the toolchain accurate timing and power models for the DVFS block and for the resynchronization logic between different Voltage and Frequency Islands (VFIs). In such a way, a more accurate validation of novel optimization methodologies which exploit such actuator is possible, since both architectural and actuator overheads are considered at the same time. This work proposes a complete cycle accurate framework for multi-core design supporting Global Asynchronous Local Synchronous (GALS) NoC design and DVFS actuators for the NoC. Furthermore, static and dynamic frequency assignment is possible with or without the use of the voltage regulator. The proposed framework sits on accurate analytical timing model and

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RAFT: A router architecture with frequency tuning for on-chip networks

Cited by 25 publications

References 27 publications

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

An energy-efficient multi-level RF-interconnect for global network-on-chip communication

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

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