Raman Study of Multicrystalline Silicon Wafers Produced by the RST Process

Abstract

In the silicon ribbon on a sacricial template process silicon is deposited on both sides of a carbon ribbon, thus forming a Si/carbon/Si trilayer. The fast cooling of the ribbon in large temperature gradients generates stresses that are detrimental to both the electrical performance and the mechanical behaviour of the wafers. The assessment of the stresses is crucial for the setting-up of thermal treatments allowing for the stress relaxation of the wafers, prior to the cell fabrication. We present an analysis of the stress in the as-grown trilayer by a simulation of the thermomechanical behaviour of the cooling ribbon. Experimental measurements of the stress in as-grown and annealed trilayers are also presented. The results permit to establish the conditions for optimized growth and annealing.

Analysis of the reduction of tensile stress by post‐growth annealing methods in multicrystalline silicon wafers produced by the RST process

“…The laser cutting yield concerns the fraction of crack-free wafers, 50 mm wide, extracted from ribbons 55 mm in width. In a previous work we studied the influence of the post-growth heater configuration (H p , T p and τ p ) on the stress relaxation [8]. A remarkable increase of the laser cutting yield after in-line annealing was observed.…”