Random projection for spike sorting: Decoding neural signals the neural network way

Patil, Aakash; Shen, Shanlan; Yao, Enyi; Basu, Arindam

doi:10.1109/biocas.2015.7348411

Cited by 6 publications

(10 citation statements)

References 9 publications

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“…From training, we know only M = 4749 neurons are cognizant and hence while testing, we do not waste resource for further operations on them. To create zero-mean random vectors, we need to perform 4749 pairwise subtractions in a method similar to [16]. Since we plan to use tristate non-linearity, ELM 2nd stage is just 4749×10 addition/subtraction operation of 10 sets of output weights.…”

Section: Energy Efficiencymentioning

confidence: 99%

“…Of these, [15] shows the application of ELM to a single input single output regression problem. On the other hand, [16,17] have already shown good accuracy at the system level for applications like intention decoding [17] and spike sorting [16] requiring multiple inputs and outputshence, we pursue this architecture further. The first novelty of this paper is in applying such a hardware to image based object recognition applications.…”

Section: Introductionmentioning

confidence: 99%

“…The first novelty of this paper is in applying such a hardware to image based object recognition applications. With image pixels represented as digital values, we used digital input ELM (D-ELM) IC of [16] for our purpose. But, object recognition needs a very large number of hidden neurons to achieve high accuracy-due to space constraints, this may be difficult to have in hardware.…”

Section: Introductionmentioning

confidence: 99%

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Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition

et al. 2017

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We demonstrate a low-power and compact hardware implementation of Random Feature Extractor (RFE) core. With complex tasks like Image Recognition requiring a large set of features, we show how weight reuse technique can allow to virtually expand the random features available from RFE core. Further, we show how to avoid computation cost wasted for propagating "incognizant" or redundant random features. For proof of concept, we validated our approach by using our RFE core as the first stage of Extreme Learning Machine (ELM)-a two layer neural network-and were able to achieve > 97% accuracy on MNIST database of handwritten digits. ELM's first stage of RFE is done on an analog ASIC occupying 5mm×5mm area in 0.35µm CMOS and consuming 5.95 µJ/classify while using ≈ 5000 effective hidden neurons. The ELM second stage consisting of just adders can be implemented as digital circuit with estimated power consumption of 20.9 nJ/classify. With a total energy consumption of only 5.97 µJ/classify, this low-power mixed signal ASIC can act as a co-processor in portable electronic gadgets with cameras.

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Section: Energy Efficiencymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition

et al. 2017

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“…Hence, there would not be more resource induced. The performance of spike sorting with our ELM classifier is shown in [94].…”

Section: Discussionmentioning

confidence: 99%

“…Since we have successfully implemented the ELM in the hardware for a variety of applications, we can utilize this ELM in the process of neural recording for spike sorting and intention decoding. Measurement have been conducted for spike sorting using our proposed ELM chip [94]. In the future, an integration of spike detection, spike sorting and machine learner based classifier can be designed for the neural recording system.…”

Section: Future Workmentioning

confidence: 99%

Low power smart sensor circuits for biomedical applications : applications to neural interfaces

Yao¹

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mark binary classification datasets have been employed in the measurement showing that the performance of our design is comparable with recent publications and software simulations of other machine learning system. This system was implemented in a 0.35 µm CMOS process which can operate from 0.8 V to 3.3 V power supply with a lowest classification energy 0.47 nJ/op and maximum classification speed 518 MMAC/s. v vi

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Big Data Management in Neural Implants: The Neuromorphic Approach

Basu

Chen

Yao

2017

Emerging Technology and Architecture for Big-Data Analytics

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Random projection for spike sorting: Decoding neural signals the neural network way

Cited by 6 publications

References 9 publications

Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition

Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition

Low power smart sensor circuits for biomedical applications : applications to neural interfaces

Big Data Management in Neural Implants: The Neuromorphic Approach

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