Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit

Mukherjee, Chhandak; Jacquet, Thomas; Chakravorty, Anjan; Zimmer, Thomas; Boeck, J.; Aufinger, Klaus; Maneux, Cristell

doi:10.1016/j.microrel.2017.05.001

Cited by 4 publications

(3 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Hereinafter, a comprehensive analysis of the RTS noise in IFX SiGe:C HBTs is presented, in which dominant G-R mechanisms are evidenced at low bias currents in smaller geometries, as confirmed by RTS noise measurements [Muk17]. In larger geometries the RTS noise is not so frequently observed.…”

Section: Low-frequency Noise Characterizationmentioning

confidence: 78%

5. Reliability

2018

Southeast Asian Ephemeris

View full text Add to dashboard Cite

Section: Low-frequency Noise Characterizationmentioning

confidence: 78%

5. Reliability

2018

Southeast Asian Ephemeris

View full text Add to dashboard Cite

“…Low frequency noise and random telegraph signal are sensitive metrics for determining defects in the active devices [13,14,15], as it can reveal defects prior to any stress application, while most electrical characterization setups are not able to track those defects (except for DLTS measurement techniques). For long-term operation, the main reliability issue in SiGe HBTs is the cumulative degradation of the base current that occurs under combined high emitter current and high collector voltage stress.…”

Section: Electrical and Lfn Measurements And Models For Reliability Cmentioning

confidence: 99%

Non-destructive techniques for evaluating the reliability of high frequency active devices

Tartarin

2019

Microelectronics Reliability

View full text Add to dashboard Cite

SiGe and GaN technologies have achieved rapid development over the last two decades. High level of RF circuit integration on Si low cost substrates open the way for large development of SiGe HBTs, while needs for high power density make GaN HEMT a key technology for solid state power modules. As both of these technologies achieve very elevated frequencies, they become strong contenders to GaAs technologies. Then reliability studies are needed to improve the process at the lower technology readiness level scale, and to stabilize the technological process till the final qualification step. To make an efficient diagnostic on the causal origin of the physical root mechanisms involved during the application of a stress, a multi-tool approach is mandatory to secure the diagnostic. In this paper, case studies on SiGe HBT and GaN HEMT stressed devices are proposed through the cross-analysis of low frequency noise spectral densities, of electrical transient measurements, and of TCAD simulations.

show abstract

“…The DIR models also include a safe operating area (SOA) models [14][15][16] which are used to check the stress on the MOS terminals. By increasing voltage difference between any two terminals of MOS devices stress rises which can enhance the effect of HCI, NBTI and TDDB degradation.…”

Section: Introductionmentioning

confidence: 99%

Programmable CCCII: reliability analysis and design methodology

Tiwari

Pandey

Paul

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

In this study, an effective and efficient approach for reliability analysis is developed to bridge the gap between devicelevel reliability and that at the product level. Continual reduction of device dimensions, gate-oxide and increase in channel doping results in an increased electric field which is introducing most of the reliability concerns. Four most important reliability issues impacting circuit design are hot carrier injection, bias temperature instability, time-dependent dielectric breakdown and self-heating. As the second-generation current controlled conveyor (CCCII) circuit are used to implement oscillator, filter clock and so on, which are working continuously even in sleep mode. So it is important to take care of all the reliability aspects while designing CCCII. There is a challenge in complex design to identify which devices (MOS, resistor and capacitor) are susceptible to degradation and then redesign and mitigate this effect for a robust and reliable design. The objective of this work is to detect reliability issues and design a programmable current conveyor which can work safely for a long duration. The circuit has been designed and simulated using 28 nm CMOS technology model parameters on Cadence Virtuoso/AMS environment (ELDO simulator) using ± 1.8 V supply voltage and results have been verified with post-layout netlist.

show abstract

Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit

Cited by 4 publications

References 26 publications

5. Reliability

5. Reliability

Non-destructive techniques for evaluating the reliability of high frequency active devices

Programmable CCCII: reliability analysis and design methodology

Contact Info

Product

Resources

About