Random Yield Prediction Based on a Stochastic Layout Sensitivity Model

As the technology scales advancing into the nanometer region, the concept of yield has become an increasingly important design metric. To reduce the yield loss caused by local defects, layout optimization can play a critical role. In this paper, we propose a new open sensitivity-based model with consideration of the blank space around the net, and study the corresponding net optimization. The proposed new model not only has a high practicability in the selection of nets to be optimized but also solves the issue of the increase in short critical area brought during the open optimization,which means to reduce the open critical area with no new short critical area produced, and thereby this model can ensure the decrease of total critical area and finally achieves an integrative optimization. Compared with the models available, the experimental results show that our sensitivity model not only consumes less time with concise algorithm but also can deal with irregular layout, which is out of the scope of other models. At the end of this paper, the effectiveness of the new model is verified by the experiment on the randomly selected five metal layers from the synthesized OpenSparc circuit layout.

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“…An open sensitivity model is used in Ref. [37], which uses very basic layout information. The channel density is indicated by the letter d ,…”

Section: Sensitivity Model Based On Very Basic Layout Informationmentioning

confidence: 99%

“…In Ref. [37], this layout sensitivity model based on the layout information is focused on the prediction of random yield, but its application in layout optimization is not described, and this model does not consider the real defect and the network shape. Moreover, in Ref.…”

Section: Introductionmentioning

confidence: 99%

A new sensitivity model with blank space for layout optimization^*

Wang

Liu

et al. 2017

J. Semicond.

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“…There are such blocks mapped on the first corrective bank, and therefore the probability that the MUR is fully repaired is given by (2) A spare word of the second corrective bank maps a pair of blocks that are already mapped on two spare words of the first corrective bank. The block pair is repairable by the second corrective bank, if it has at most one faulty word, which is the probability that at most one faulty word cannot be repaired by the first corrective bank.…”

Section: A Random Faultsmentioning

confidence: 99%

“…than logic. Yield estimates are associated with defect density and critical area [2] (area where a potential defect kills the product) and therefore memory components are unintentionally yieldlimiters by design. Although progress in clean-room facilities has greatly reduced traditional particle induced defects, the relentless feature miniaturization is guided by new lithography techniques that offer the much needed resolution enhancement, while introducing new types of defect sources.…”

Section: Introductionmentioning

confidence: 99%

Efficient Memory Repair Using Cache-Based Redundancy

Axelos

Pekmestzi

Gizopoulos

2012

IEEE Trans. VLSI Syst.

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In modern processes, conventional defect density and variability related yield losses are a major concern for the aggressive memory designs in integrated circuits. Synergistic action for memory repair at the circuit and architectural level is essential to maintain the yields and profitability of past technology nodes. In this paper, we propose a scalable memory repair architecture that utilizes a set of direct-mapped cache banks to replace faulty words. Statistical and mathematical probability analysis shows that the proposed scheme achieves high repairability levels with low area and static power dissipation overheads, the latter being a dominant issue in nanometer technologies. It is therefore a suitable solution along with other mature memory repair techniques, to enhance the overall repairability features and guarantee the correct and reliable operation of embedded memories in nanometer technologies.

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“…According to Ref. [1], the layout's sensitivity to defects almost doubles every three technology generations. As the most important metric of IC layout's sensitivity to defects, the critical area is widely used to predict a chip's yield OE2; 3 .…”

Section: Introductionmentioning

confidence: 99%

An improved shape shifting method of critical area extraction

Zhu¹,

Luo²,

Chen³

et al. 2014

J. Semicond.

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As die size and complexity increase, accurate and efficient extraction of the critical area is essential for yield prediction. Aiming at eliminating the potential integration errors of the traditional shape shifting method, an improved shape shifting method is proposed for Manhattan layouts. By mathematical analyses of the relevance of critical areas to defect sizes, the critical area for all defect sizes is modeled as a piecewise quadratic polynomial function of defect size, which can be obtained by extracting critical area for some certain defect sizes. Because the improved method calculates critical areas for all defect sizes instead of several discrete values with traditional shape shifting method, it eliminates the integration error of the average critical area. Experiments on industrial layouts show that the improved shape shifting method can improve the accuracy of the average critical area calculation by 24.3% or reduce about 59.7% computational expense compared with the traditional method.

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Random Yield Prediction Based on a Stochastic Layout Sensitivity Model

Cited by 12 publications

References 30 publications

A new sensitivity model with blank space for layout optimization^*

A new sensitivity model with blank space for layout optimization^*

Efficient Memory Repair Using Cache-Based Redundancy

An improved shape shifting method of critical area extraction

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Random Yield Prediction Based on a Stochastic Layout Sensitivity Model

Cited by 12 publications

References 30 publications

A new sensitivity model with blank space for layout optimization*

A new sensitivity model with blank space for layout optimization*

Efficient Memory Repair Using Cache-Based Redundancy

An improved shape shifting method of critical area extraction

Contact Info

Product

Resources

About

A new sensitivity model with blank space for layout optimization^*

A new sensitivity model with blank space for layout optimization^*