Range Translations for Fast Virtual Memory

Gandhi, Jayneel; Karakostas, Vasileios; Ayar, Furkan; Cristal, Adrián; Hill, Mark D.; McKinley, Kathryn S.; Nemirovsky, Mario; Swift, Michael M.; Ünsal, Osman

doi:10.1109/mm.2016.10

Cited by 33 publications

(15 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Second, for most applications, the total number of segments and the number of segments needed for 99% coverage are much higher than what the RMM work assumes. On average, even for the small 8GB dataset, the total number of segments is 4× higher, and the number of segments for 99% coverage is almost an order of magnitude higher than the requirements for the applications evaluated in [36]. The total number of segments places a burden on the number of range TLB entries.…”

Section: B Resultsmentioning

confidence: 96%

“…As for the data-structure kernels, DIPTA clearly outperforms conventional translation hardware, while virtually delivering the performance of an ideal translation with a perfect TLB. 4) Comparison with Other Proposals: Two recent proposals on address translation for CPUs are direct segments (DS) [21] and redundant memory mappings (RMM) [36]. These approaches exploit the abundant contiguity available in the virtual address space of certain applications by mapping one (for DS) or a few (for RMM) virtual segments to contiguous page frames.…”

Section: B Resultsmentioning

confidence: 99%

“…We focus on workloads whose working set fits (almost) entirely in memory. We believe this scenario is the common case as memory is growing exponentially cheaper and bigger [36], while modern online services and analytic engines consistently require low response times [7], [9], [21], [25], [35], [41], [57], [67], [76], [95]. Nevertheless, prior work on multi-GB caches backed up with an order-of-magnitude larger DRAM memory, has shown little sensitivity to associativity [48], [78].…”

Section: Discussionmentioning

confidence: 98%

See 2 more Smart Citations

Near-Memory Address Translation

Picorel¹,

Jevdjic

Falsafi³

2017

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)

View full text Add to dashboard Cite

Abstract-Memory and logic integration on the same chip is becoming increasingly cost effective, creating the opportunity to offload data-intensive functionality to processing units placed inside memory chips. The introduction of memoryside processing units (MPUs) into conventional systems faces virtual memory as the first big showstopper: without efficient hardware support for address translation MPUs have highly limited applicability. Unfortunately, conventional translation mechanisms fall short of providing fast translations as contemporary memories exceed the reach of TLBs, making expensive page walks common.In this paper, we are the first to show that the historically important flexibility to map any virtual page to any page frame is unnecessary in today's servers. We find that while limiting the associativity of the virtual-to-physical mapping incurs no penalty, it can break the translate-then-fetch serialization if combined with careful data placement in the MPU's memory, allowing for translation and data fetch to proceed independently and in parallel. We propose the Distributed Inverted Page Table (DIPTA), a near-memory structure in which the smallest memory partition keeps the translation information for its data share, ensuring that the translation completes together with the data fetch. DIPTA completely eliminates the performance overhead of translation, achieving speedups of up to 3.81× and 2.13× over conventional translation using 4KB and 1GB pages respectively.

show abstract

Section: B Resultsmentioning

confidence: 96%

Section: B Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 98%

See 1 more Smart Citation

Near-Memory Address Translation

Picorel¹,

Jevdjic

Falsafi³

2017

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)

View full text Add to dashboard Cite

show abstract

“…Research has shown that TLB miss processing is prohibitively expensive [21,24,25,26,38,53] as walking pagetables (e.g., 4-level radix tree on x86-64) requires multiple memory accesses. Even worse, virtualized systems need twolevels of page-table lookups which can result in much higher TLB miss processing overheads (24 memory accesses instead of four on x86-64).…”

Section: Virtual Memorymentioning

confidence: 99%

Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines

Achermann

Panwar²,

Bhattacharjee

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

Self Cite

View full text Add to dashboard Cite

Multi-socket machines with 1-100 TBs of physical memory are becoming prevalent. Applications running on multi-socket machines suffer non-uniform bandwidth and latency when accessing physical memory. Decades of research have focused on data allocation and placement policies in NUMA settings, but there have been no studies on the question of how to place page-tables amongst sockets. We make the case for explicit page-table allocation policies and show that pagetable placement is becoming crucial to overall performance.We propose Mitosis to mitigate NUMA effects on page-table walks by transparently replicating and migrating page-tables across sockets without application changes. This reduces the frequency of accesses to remote NUMA nodes when performing page-table walks. Mitosis uses two components: (i) a mechanism to enable efficient page-table replication and migration; and (ii) policies for processes to efficiently manage and control page-table replication and migration.We implement Mitosis in Linux and evaluate its benefits on real hardware. Mitosis improves performance for large-scale multi-socket workloads by up to 1.34x by replicating pagetables across sockets. Moreover, it improves performance by up to 3.24x in cases when the OS migrates a process across sockets by enabling cross-socket page-table migration.

show abstract

“…Direct segments [15,34] extend standard paging with a large segment to map the majority of address space to a contiguous physical memory region but require application modications and are limited to workloads able to a single large segment. Redundant memory mappings [7,37,52] extend TLB reach by mapping ranges of virtually and physically contiguous pages in a range TLB.…”

Section: Related Workmentioning

confidence: 99%

Prism

Ausavarungnirun

Merrifield

Gandhi

et al. 2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

Self Cite

View full text Add to dashboard Cite

Modern architectures track memory accesses using page granularity metadata such as access and dirty bits, leading to fundamental tradeos for system software that uses this metadata. Larger page sizes reduce address translation overheads and page table footprints. However, coarse metadata bits for larger pages limit software's visibility into application-level memory usage, resulting in memory bloat and performance pathologies. As DRAM capacity continues to expand, we expect software to react by aggressively mapping with larger page sizes, making this tradeo space more challenging to navigate. We study the relationship between metadata granularity and delity, the degree to which metadata correctly approximates actual access patterns. We focus on 2MB page support on x86-64 and GPUs, measuring delity across a wide range of benchmarks. Fidelity can be poor at a coarse granularity, and high variance occurs even within applications. To address this problem, we propose P, which provides architectural support for variable-granularity access and dirty bits. Evaluation of Linux/x86-64 and GPU prototypes of P show modest additional hardware can reduce metadata delity loss by up to 65% and 55% at a performance cost of less than 1% and 2% on CPUs and GPUs respectively. We show that the recovered delity can eliminate performance pathologies and improve the performance of GPGPU applications using demand paging by 29.8% on average. CCS CONCEPTS • Software and its engineering ! Virtual memory; • Computer systems organization ! Parallel architectures.

show abstract

Range Translations for Fast Virtual Memory

Cited by 33 publications

References 8 publications

Near-Memory Address Translation

Near-Memory Address Translation

Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines

Prism

Contact Info

Product

Resources

About