Rapid Evolution of Time-Efficient Packet Classifiers

Abstract

Communication networks today are facing an ever increasing network traffic as well as raising quality-of-service agreements, which together demand for high performance network routers. Since a router has to search a large set or routing rules for every incoming packet, it normally utilizes efficient search mechanisms, such as trees or hash tables. This paper evolves hash functions directly in hardware and also discusses an improved initialization process. On a benchmark test consisting of 65,536 routing rules, the final hash functions consume an average of about 1.3 memory accesses for rule searching for every incoming data packet.

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

“…Application Reconfiguration FPGA EA Fitness [37] FIR filters Register values Any, not reported HW HW [21] Image filters VRC XC2V3000 HW HW [28] Hash functions VRC XC4VFX20 HW HW [38] RBN a /Cellular automaton LUT-DPR (ICAP) Virtex-II MicroBlaze MBlaze [39] Image filters VRC XC2VP50 PowerPC HW [13] Sonar spectrum classifier VRC XC2VP30 PowerPC HW [44] Arith. circuits VRC XCV2000E HW 2×HW [40] CGP accelerator VRC XC2VP50 PowerPC HW [10] Face image classif.…”

“…Typical architectures for FPGA-based evolvable systems closely follows general IPbased designs for FPGAs using a central processor, which holds the EA, and different hard-IP cores, among which an evolvable component is included. Complete hardware evolution experiments in which the EA is also implemented in HW have also been conducted [37,21,28,44,43,42]. However, these were mostly abandoned given: (i) the advantages for fine tuning the EA using an embedded processor; and (ii) the fact that the fitness computation is the most time consuming task, so no significant speed-ups are obtained with a HW implementation of the EA for most applications reported.…”

Evolutionary functional recovery in virtual reconfigurable circuits

“…The following list shows examples of evolvable systems which were implemented using the idea of the VRC on an FPGA: -evolvable image filter for the evolution of 3x3 image operators (EA is implemented either in PC [Zhang et al 2004] or on the same FPGA as a special circuit [Martinek and Sekanina 2005] or in an on-chip PowerPC processor [Vasicek and Sekanina 2007]); -evolvable sorting network for up to 28 inputs (EA is implemented on the same FPGA) [Korenek and Sekanina 2005]; -evolvable combinational circuits (EA is implemented on the same FPGA as a special circuit [Sekanina and Friedl 2004] or in the PowerPC processor on the same FPGA [Glette and Torresen 2005]); -intrinsic evolution of polymorphic combinational modules (EA is implemented on the same FPGA) ]; -evolvable IIR filter (EA is implemented on a DSP) [Gwaltney and Dutton 2005]; -packet classifiers (EA is implemented as a special circuit on the same FPGA) [Salomon et al 2006]. …”

“…Because a designer can construct the VRC so that it exactly fits the needs of a given evolvable hardware-based application, a perfect reconfigurable device can be obtained for a given problem. Examples include VRCs for the evolution of logic circuits [Sekanina and Friedl 2004], image filters [Martinek and Sekanina 2005], IIR filters [Gwaltney and Dutton 2005], sorting networks [Korenek and Sekanina 2005], or packet classifiers [Salomon et al 2006]. As the evolutionary algorithm can be implemented on the same FPGA (as an application-specific circuit or in a processor) in these applications, a fast configuration interface can be established connecting the configuration memory of VRC with chromosomes of EA.…”

Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling

“…Internal reconfiguration [19] FIR filters [20] Logic circuits [21] Image filters [22] Hash functions [23] Cellular automaton [24] Image filters [25] CGP accelerator [26] Face recognition [27] Sonar spectrum class [28] Arith. circuits [29] Image filters, classif.…”