RAPID for high-performance computing systems: architecture and performance evaluation

Abstract

The limited bandwidth and the increase in power dissipation at longer communication distances and higher bit rates will create a major communication bottleneck in high-performance computing systems (HPCS), affecting not only their performance, but also their scalability. As a solution, we propose an optical-interconnect-based architecture for HPCS called reconfigurable all-photonic interconnect for parallel and distributed systems (RAPID) that alleviates the bandwidth density, optimizes power consumption, and enhances scalability. We also present two cost-effective design alternatives of the architecture, a modified version called M-RAPID and an extended version called E-RAPID that minimizes the cost of the interconnect based on the number of transmitters required. We perform a detailed simulation of the proposed RAPID architecture and compare it to several electrical HPCS interconnects. Based on the performance study, RAPID architecture shows 30%-50% increased throughput and 50%-75% reduced network latency as compared to HPCS electrical networks.

Efficient Dynamic Bandwidth Re-allocation in Photonic Networks using SOI-based Microring Resonators

“…RAPID (Reconfigurable All-Photonic Interconnected for Distributed parallel computers) is an opto-electronic network designed for HPC systems [3] as shown in Figure 1(a). Although static routing and wavelength assignment proposed in RAPID provides good performance for uniform and benign traffic patterns, considerable degradation in system performance is observed for adversial traffic due to uneven resource utilization.…”

“…Dynamic bandwidth reallocation (DBR) technique adapts to traffic patterns by re-allocating bandwidth from under-utilized links to overutilized links. For RAPID architecture [3], we eliminate AWGs and replace them with row-column switches as shown in Figure 1(b). The row and column switches are themselves 2 × 2 switches.…”

Reconfigurable and adaptive photonic networks for high-performance computing systems

“…In modified (M)-RAPID, the processors have electrical links for intraboard communication and optical links for interboard. In electrical (E)-RAPID, electrical onboard communication is used for both intraboard and interboard (up to optical transmitters and receivers) [16]. This allowed us to reduce the cost of the network without excessive optical signaling.…”

“…Scalable Design: E-RAPID provides several scalable features including the incremental addition of wavelengths, nodes, and boards. Various design choices that enable high bandwidth, low latency, and reasonable cost in E-RAPID have cumulatively resulted in providing maximum flexibility for scaling [16].…”

“…These topologies are the most common clustering interconnects, for example, the 2-D torus is used in the Alpha 21364 network [26]; the hypercube is used in the SGI Spider chip used for SGI Origin machines [27]; and the fat-tree topology is the basis of most Mellanox switches used in Infiniband architectures [28] as well as in Elan 2 used in QsNet [25]. In addition, we compared E-RAPID with two other RAPID topologies, RAPID and M-RAPID architectures [16]. While RAPID is an all-photonic network, M-RAPID replaces optics with electronics for the intraboard interconnect for local communication only.…”