Rapid Generation of Thermal-Safe Test Schedules

Rosinger, P.; Al-Hashimi, Bashir M.; Chakrabarty, Krishnendu

doi:10.1109/date.2005.252

Cited by 28 publications

(44 citation statements)

References 13 publications

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“…The process of heat transfer of node i is described with a RC-thermal model [21], [22], [23]. As shown in Figure 4, P denotes the power consumption of compute node at current time t, C is the thermal capacitance of the compute node, R denotes the thermal resistance, and T emp(node i .…”

Section: Choosing An Optimal Configurationmentioning

confidence: 99%

Towards Thermal Aware Workload Scheduling in a Data Center

Wang

Laszewski

Dayal

et al. 2009

2009 10th International Symposium on Pervasive Systems, Algorithms, and Networks

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Abstract-High density blade servers are a popular technology for data centers, however, the heat dissipation density of data centers increases exponentially. There is strong evidence to support that high temperatures of such data centers will lead to higher hardware failure rates and thus an increase in maintenance costs. Improperly designed or operated data centers may either suffer from overheated servers and potential system failures, or from overcooled systems, causing extraneous utilities cost. Minimizing the cost of operation (utilities, maintenance, device upgrade and replacement) of data centers is one of the key issues involved with both optimizing computing resources and maximizing business outcome.This paper proposes an analytical model, which describes data center resources with heat transfer properties and workloads with thermal features. Then a thermal aware task scheduling algorithm is presented which aims to reduce power consumption and temperatures in a data center. A simulation study is carried out to evaluate the performance of the algorithm. Simulation results show that our algorithm can significantly reduce temperatures in data centers by introducing endurable decline in performance.

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Section: Choosing An Optimal Configurationmentioning

confidence: 99%

Towards Thermal Aware Workload Scheduling in a Data Center

Wang

Laszewski

Dayal

et al. 2009

2009 10th International Symposium on Pervasive Systems, Algorithms, and Networks

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“…Usually, test power of circuit is much higher than functional power as much as two to five times higher [1]. In some cases, the peak power of test even reaches up to 30 times higher of the functional power [2].…”

Section: Introductionmentioning

confidence: 99%

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Tian

Shen

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYLinear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, Xfilling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

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“…In Section 2 we present an algorithm which determines the appropriate scan shift frequency for each test session in order to minimize the overall testing time and improve the ability to generating hot-spot free test schedules under very tight thermal constraints. Scan shift frequency scaling also resolves eventual thermal violations, issue which was not explicitly addressed in approach presented in [15]. An added advantage of this solution is that it does not require any modification of the embedded cores which was indicated as a potential solution in [15].…”

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confidence: 99%

“…The second category of techniques is mainly based on power-constrained test scheduling algorithms [2,8,10,7,6,1,13,11,12] and the recently proposed thermal-safe test scheduling algorithms [15]. Unlike power-constrained test scheduling approaches, the thermal-safe test scheduling method we have presented in [15] guarantees hot-spotfree test schedules by ensuring that a given critical die temperature is not exceeded during test. This is possible by limiting the maximum test concurrency in each test session based on the thermal behaviour of the cores under test rather than on their power consumption.…”

mentioning

confidence: 99%

“…Techniques falling in the first category include low-power scan chain architectures with gated clocks [16,4,14], scan cell and test pattern reordering [3,5], and low-transition test patterns generated by specialized ATPG algorithms [19] and low-transition TPGs [18]. The second category of techniques is mainly based on power-constrained test scheduling algorithms [2,8,10,7,6,1,13,11,12] and the recently proposed thermal-safe test scheduling algorithms [15]. Unlike power-constrained test scheduling approaches, the thermal-safe test scheduling method we have presented in [15] guarantees hot-spotfree test schedules by ensuring that a given critical die temperature is not exceeded during test.…”

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confidence: 99%

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