Rapid runtime estimation methods for pipelined MPSoCs

Abstract

The pipelined Multiprocessor System on Chip (MPSoC) paradigm is well suited to the data flow nature of streaming applications. A pipelined MPSoC is a system where processing elements (PEs) are connected in a pipeline. Each PE is implemented using one of a number of processor configurations (configurations differ by instruction sets and cache sizes) available for that PE. The goal is to select a pipelined MPSoC with a mapping of a processor configuration to every PE. To estimate the runtime of a pipelined MPSoC, designers typically perform cycle-accurate simulation of the whole pipelined system. Since the number of possible pipelined implementations can be in the order of billions, estimation methods are necessary.In this paper, we propose two methods to estimate the runtime of a pipelined MPSoC, minimizing the use of slow cycle-accurate simulations. The first method estimates the runtime of the pipelined MPSoC, by performing cycle accurate simulations of individual processor configurations (rather than the whole pipelined system), and then utilizing an analytical model to estimate the runtime of the pipelined system. In the second method, runtimes of individual processor configurations are estimated using an analytical processor model (which uses cycleaccurate simulations of selected configurations, and an equation based on ISA and cache statistics). These estimated runtimes of individual processor configurations are then used to estimate the total runtime of the pipelined system. By evaluating our approach on three benchmarks, we show that the maximum estimation error is 5.91% and 16.45%, with an average estimation error of 2.28% and 6.30% for the first and second method respectively. The time to simulate all the possible pipelined implementations (design points) using cycle-accurate simulator is in the order of years, as design spaces with at least 10 10 design points are considered in this paper. However, the time to simulate all processor configurations individually (first method) takes tens of hours, while the time to simulate a subset of processor configurations and estimate their runtimes (second method) is only a few hours. Once these simulations are done, the runtime of each pipelined implementation can be estimated within milliseconds.

Falcon

“…They proposed a statistical model to estimate the total energy saving of L2 cache and DRAM memory when L2 cache is changed and lowpower mode is used for DRAM during its idle periods. Figure 6 Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile Tile [24] proposed two methodologies to estimate execution time of a SoC consisting of multiple processors connected in a pipeline with hardware buffers in between. An example SoC from their paper is shown in Figure 6(b), with a total of 1.72 × 10 12 design points.…”

“…We chose SoCs, their estimation methodologies and component models from existing works [23,24,25] because we were able to reproduce those works.…”

“…Same execution schedule is used for the other PEs as well. For both estimation methodologies of [24], FALCON automatically executed the models in the correct order with minimal executions.…”

“…[ # se l f -co n f i g s. # d e si g n p o i n t s]Figure 6: Application of FALCON to (a) uniprocessor SoC[23] (b) multiprocessor pipeline SoC[24] (c) multiprocessor mesh NoC SoC[25].for all the 330 cache configurations. The authors of[23] manually determined the number and order of model executions, where as FALCON automatically executed these models in the correct order with minimal executions to gather the energy savings of all the design points, reducing designer's effort.…”

Performance Estimation of Task Graphs Based on Path Profiling

“…For example, [12] exploits the intermediate representation of the SUIF compiler [24] to estimate the execution time of each task and, then, interval analysis to predict the execution time of the whole application. In a similar way, in [25], GCC is modified to automatically generate the workload models of the tasks, while [26] combines performance estimation of single processors to estimate the performance of JPEG encoder and decoder applications on a pipelined MPSoC. [27] considers an ILP formulation for automatically parallelizing a hierarchical task graph representation, but the cost estimation is performed by simply associating a weight with each instruction, without analyzing the correlations between the control constructs.…”