Rapid single-flux-quantum dual-rail logic for asynchronous circuits

Maezawa, M.; Kurosawa, I.; Aoyagi, Masahiro; Nakagawa, Hiroshi; Kameda, Yusuke; Nanya, Takashi

doi:10.1109/77.621796

Cited by 29 publications

(13 citation statements)

References 9 publications

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“…The DFFC is the important circuit component of the SFQ decoder, which is indispensable to build memory system [26][27][28]. The SFQ flip-flops with complementally outputs containing -JJs can be also applied to processing dual-rail SFQ data [29][30][31]. Therefore, The SFQ flip-flops containing -JJs are expected to play the important role in the large-scale SFQ memory systems and asynchronous and ultra-low power dualrail SFQ logic circuits.…”

Section: Delay Flip-flop With Complementally Outputsmentioning

confidence: 99%

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Yamanashi

Nakaishi

Yoshikawa

2019

IEEE Trans. Appl. Supercond.

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We designed several single flux quantum (SFQ) flipflops and logic gates composed of Josephson junctions (JJs) and shifted JJs (-JJs) to quantitatively evaluate effectiveness of introduction of -JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing -JJs. The designed flip-flops and logic gates have wide operating margins, the dc bias margins of larger than ±30% and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and -JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and -JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and -JJs (-DFFC). The analog circuit simulation shows the dc-bias margin of the -DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing -JJs.  Index Terms-Single-flux-quantum (SFQ) circuit, -shifted Josephson junction, flip-flop I. INTRODUCTION NERGY Consumption for Information and Communication Technology (ICT) has drastically increased for decades.Total energy consumption for ICT devices in the world has already reached 1 PWh/year in 2017, which is larger than annual energy consumption in Japan, and is estimated to keep increasing in the future [1]. However, semiconductor integrated circuit technology, which has been supporting the ICT development, is facing several obstacles [2]. Among the obstacles, power consumption is the most serious problem of the semiconductor complementary metal-oxide-semiconductor (CMOS) integrated circuit. In this sort of situation, beyond-CMOS devices that can overcome limitation of CMOS devices, have been studied [3]. Among various beyond-CMOS devices, superconducting digital devices, including single-fluxquantum (SFQ) devices [4,5] and its improved versions have a high-speed operation characteristic with ultra-high energy ef-Manuscript receipt and acceptance dates will be inserted here.

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Section: Delay Flip-flop With Complementally Outputsmentioning

confidence: 99%

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Yamanashi

Nakaishi

Yoshikawa

2019

IEEE Trans. Appl. Supercond.

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“…RSFQ deserializers (demultiplexers) generally follow two different approaches: a binary tree [30,37,[54][55][56][57][58] or a shift-and-dump [59][60][61] architecture. For conversion to eSFQ, we chose the latter approach as it has found more applications in practical circuits due to its high modularity and simple timing.…”

Section: Esfq Deserializer-edesmentioning

confidence: 99%

Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation

Volkmann

Sahu

Fourie

et al. 2012

Supercond. Sci. Technol.

142

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We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm 2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.

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“…Two types of RSFQ DMUX have been proposed and demonstrated so far. One is based on the binary tree architecture [4][5][6][7][8][9][10] and the other is based on the shift-anddump architecture [3]. The binary tree type DMUX has been more widely investigated.…”

Section: Architecturementioning

confidence: 99%

“…A practical way of transmitting data is to down-convert high-speed RSFQ data into sufficiently low-speed ones. Thus, a demultiplexer (DMUX) [3][4][5][6][7][8][9][10] is a key subsystem for practical use of RSFQ circuits and systems.…”

Section: Introductionmentioning

confidence: 99%

Design and operation of a rapid single flux quantum demultiplexer

Maezawa

Suzuki

Shoji

2002

Supercond. Sci. Technol.

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A demultiplexer (DMUX) is a key subsystem of rapid single flux quantum (RSFQ) circuits and systems in practical applications. High-speed data from RSFQ circuits should be converted into sufficiently low-speed ones for transmission to and processing by room temperature electronics. We designed, fabricated and successfully tested an RSFQ DMUX based on the synchronous shift-and-dump architecture whose advantages are modularity and compactness. A 1-to-8 DMUX was implemented using our standard cell library on 1.6 kA cm −2 Nb trilayer technology. Fully functional operation was confirmed by low speed testing. Experimental bias margins were as large as ±16%. Results of average voltage measurements implied that the DMUX was operated at data rates up to 25 Gb s −1 .

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Rapid single-flux-quantum dual-rail logic for asynchronous circuits

Cited by 29 publications

References 9 publications

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation

Design and operation of a rapid single flux quantum demultiplexer

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