Rapid synthesis and simulation of computational circuits in an MPPA

Abstract

A computational circuit is custom-designed hardware which promises to offer maximum speedup of computationally intensive software algorithms. However, the practical needs to manage development cost and many low-level physical design details erodes much of the potential speedup by distracting attention away from high-level architectural design. Instead, designers need an inexpensive, processor-like platform where computational circuits can be rapidly synthesized and simulated. This enables rapid architectural evolution and mitigates the risk of producing custom hardware. In this paper we present a tool flow (RVETool) for compiling computational circuits into a massively parallel processor array (MPPA). We demonstrate the CAD runtime is on average 70x faster than FPGA tools, with a circuit speed 6.4x slower than FPGA devices. Unlike the fixed logic capacity of FPGAs, RVETool can trade area for simulation performance by targeting a wide range of processor cores.

A CAD framework for Malibu

“…Prior work [11] details RVETool, which is the coarse-grained part of the M-CAD approach. Therefore, in this paper we only include the details required for the fine-grained integration and for the new M-HOT approach.…”

“…Therefore, in this paper we only include the details required for the fine-grained integration and for the new M-HOT approach. We refer the reader to [11] for the details of the M-CAD coarse-grained synthesis.…”

“…The remaining operations are considered coarse-grained, and most map trivially onto the supported CG operations. However some require more complicated graph transformations [11] to legalize the CDFG for the architecture.…”

“…This section briefly describes each step and how the coarse-grained and finegrained resources are handled. Prior work [11] details just the CG aspects, but the FG aspects presented here are new.…”