RapidIO as a multi-purpose interconnect

Baymani, Simaolhoda; Alexopoulos, Konstantinos; Valat, S.

doi:10.1088/1742-6596/898/8/082007

Cited by 3 publications

(2 citation statements)

References 1 publication

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“…Thanks to FPGA programmable logic, it is also possible to interface hardware accelerators with space-design communication protocols, according to design requirements, such as the well-established SpaceWire [57] or the newest high-speed interfaces SpaceFibre [58,59], RapidIO [60], and TTEthernet [61]. These standards implement Fault Detection Isolation and Recovery (FDIR) mechanisms to identify and re-send data packets corrupted by incident radiation during the transmission process, without any data loss.…”

Section: Space-oriented Designmentioning

confidence: 99%

An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study

et al. 2021

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In recent years, research in the space community has shown a growing interest in Artificial Intelligence (AI), mostly driven by systems miniaturization and commercial competition. In particular, the application of Deep Learning (DL) techniques on board Earth Observation (EO) satellites might lead to numerous advantages in terms of mitigation of downlink bandwidth constraints, costs, and increment of the satellite autonomy. In this framework, the CloudScout project, funded by the European Space Agency (ESA), represents the first time in-orbit demonstration of a Convolutional Neural Network (CNN) applied to hyperspectral images for cloud detection. The first instance of this use case has been done with an INTEL Myriad 2 VPU on board a CubeSat optimized for low cost, size, and power efficiency. Nevertheless, this solution introduces multiple drawbacks due to its design not specifically being for the space environment, thus limiting its applicability to short-lifetime Low Earth Orbit (LEO) applications. The current work provides a benchmark between the Myriad 2 and our custom hardware accelerator designed for Field Programmable Gate Arrays (FPGAs). The metrics used for comparison include inference time, power consumption, space qualification, and components. The obtained results show that the FPGA-based solution is characterized by a reduced inference time, and a higher possibility of customization, but at the cost of greater power consumption and a longer Time to Market. As a conclusion, the proposed approach might extend the potential market of DL-based solutions to long-term LEO or interplanetary exploration missions through deployment on space-qualified FPGAs, with a limited cost in energy efficiency.

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Section: Space-oriented Designmentioning

confidence: 99%

An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study

et al. 2021

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“…The space community handled this problem by either adapting several existing consumer communication protocols to the stringent requirements in terms of robustness and reliability of space applications (i.e. RapidIO [4], [5]) or by the development of dedicated and application-optimized protocols, such as SpaceFibre [6], [7]. In particular, a SpaceFibre protocol implementation shall detect in real time changes in the number of active lanes of the communication link, in order to preserve data integrity and speed up the link reconnection process.…”

Section: Introductionmentioning

confidence: 99%

A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case

Nannipieri

Dinelli

Fanucci

2019

IEICE Trans. Fundamentals

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Data rate requirements, from consumer application to automotive and aerospace grew rapidly in the last years. This led to the development of a series of communication protocols (i.e. Ethernet, PCI-Express, RapidIO and SpaceFibre), which use more than one communication lane, both to speed up data rate and to increase link reliability. Some of these protocols, such as SpaceFibre, are able to detect real-time changes in the number of active lanes and to adapt the data flow appropriately, providing a flexible solution, robust to lane failures. This results in a real time varying data path in the lower layers of the data handling system. The aim of this paper is to propose the architecture of a hardware block capable of reading a fixed number of words from a host FIFO and shaping them on a real time variable number of words equal to the number of active lanes.

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Building a Spaceborne Integrated High-performance Processing and Computing Platform Based on SpaceVPX

Liu

Pang

Luan

et al. 2022

2022 International Conference on Computing, Communication, Perception and Quantum Technology (CCPQT)

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RapidIO as a multi-purpose interconnect

Cited by 3 publications

References 1 publication

An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study

An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study

A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case

Building a Spaceborne Integrated High-performance Processing and Computing Platform Based on SpaceVPX

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