Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems

Decker, Normann; Gottschling, Philip; Hochberger, Christian; Leucker, Martin; Scheffel, Torben; Schmitz, Malte; Weiß, Alexander

doi:10.1007/978-3-319-70848-5_12

Cited by 23 publications

(9 citation statements)

References 24 publications

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“…We call this fragment TeSSLa a . TeSSLa stands for Temporal Stream-Based Specification Language, and has already been used for creating monitors in FPGA hardware in Decker et al (2018) and Decker et al (2017). Our acyclic fragment TeSSLa a restricts TeSSLa to non-recursive specifications, which means that no cycles are allowed in a specification.…”

Section: Introductionmentioning

confidence: 99%

Runtime verification of real-time event streams under non-synchronized arrival

et al. 2020

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We study the problem of online runtime verification of real-time event streams. Our monitors can observe concurrent systems with a shared clock, but where each component reports observations as signals that arrive to the monitor at different speeds and with different and varying latencies. We start from specifications in a fragment of the TeSSLa specification language, where streams (including inputs and final verdicts) are not restricted to be Booleans but can be data from richer domains, including integers and reals with arithmetic operations and aggregations. Specifications can be used both for checking logical properties and for computing statistics and general numeric temporal metrics (and properties on these richer metrics). We present an online evaluation algorithm for the specification language and a concurrent implementation of the evaluation algorithm. The algorithm can tolerate and exploit the asynchronous arrival of events without synchronizing the inputs. Then, we introduce a theory of asynchronous transducers and show a formal proof of the correctness such that every possible run of the monitor implements the semantics. Finally, we report an empirical evaluation of a highly concurrent Erlang implementation of the monitoring algorithm. Keywords Stream runtime verification • Monitoring • Real-time event streams • Formal methods • Parallel event processing Torben Scheffel

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Section: Introductionmentioning

confidence: 99%

Runtime verification of real-time event streams under non-synchronized arrival

et al. 2020

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“…e monitor is decoupled from the observed system. Unlike instrumentation-based approaches [10,13], the monitor is independent of the origin of the data. Furthermore, there are no assumptions on the frequency of the inputs granted it is lower than the maximum clock frequency of the FPGA.…”

Section: Introductionmentioning

confidence: 99%

FPGA Stream-Monitoring of Real-time Properties

Baumeister

Finkbeiner

Schwenger

et al. 2019

ACM Trans. Embed. Comput. Syst.

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An essential part of cyber-physical systems is the online evaluation of real-time data streams. Especially in systems that are intrinsically safety-critical, a dedicated monitoring component inspecting data streams to detect problems at runtime greatly increases the confidence in a safe execution. Such a monitor needs to be based on a specification language capable of expressing complex, highlevel properties using only the accessible low-level signals. Moreover, tight constraints on computational resources exacerbate the requirements on the monitor. us, several existing approaches to monitoring are not applicable due to their dependence on an operating system.We present an FPGA-based monitoring approach by compiling an RTL specification into synthesizable VHDL code. RTL is a stream-based specification language capable of expressing complex real-time properties while providing an upper bound on the execution time and memory requirements. e statically determined memory bound allows for a compilation to an FPGA with a fixed size. An advantage of FPGAs is a simple integration process in existing systems and superb executing time. e compilation results in a highly parallel implementation thanks to the modular nature of RTL specifications. is further increases the maximal event rate the monitor can handle.

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“…While traditional SRV approaches process event streams without considering timing information, TeSSLa supports timestamped events natively, which allows efficient processing of streams with sparse and fine-grained event sequences. Preliminary versions of TeSSLa have already been studied with regard to their usability to monitor trace data generated by embedded tracing units of processors [10]; how to implement stream-based monitors on hardware has been studied in theory [22] and practice [11]. These versions share the basic idea of transforming timed event streams but they did not allow for recursive equations and comprised only a set of ad-hoc operators.…”

Section: Introductionmentioning

confidence: 99%

TeSSLa: Temporal Stream-Based Specification Language

Convent

Hungerecker

Leucker

et al. 2018

Lecture Notes in Computer Science

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Runtime verification is concerned with monitoring program traces. In particular, stream runtime verification (SRV) takes the program trace as input streams and incrementally derives output streams. SRV can check logical properties and compute temporal metrics and statistics from the trace. We present TeSSLa, a temporal stream-based specification language for SRV. TeSSLa supports timestamped events natively and is hence suitable for streams that are both sparse and finegrained, which often occur in practice. We prove results on TeSSLa's expressiveness and compare different TeSSLa fragments to (timed) automata, thereby inheriting various decidability results. Finally, we present a monitor implementation and prove its correctness.

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Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems

Cited by 23 publications

References 24 publications

Runtime verification of real-time event streams under non-synchronized arrival

Runtime verification of real-time event streams under non-synchronized arrival

FPGA Stream-Monitoring of Real-time Properties

TeSSLa: Temporal Stream-Based Specification Language

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