RAS design for the IBM eServer z900

Abstract

RAS design for the IBM eServer z900 The IBM eServer zSeries TM Model 900, or z900, has been designed with major enhancements for hardware reliability, availability, and serviceability (RAS) in support of the zSeries RAS strategy, the eServer self-management technologies, and the z900 design objective of continuous reliable operation. The eServer self-management technologies enable the server to protect itself, to detect and recover from errors, to change and configure itself, and to optimize itself, in the presence of problems and changes, for maximum performance with minimum outside intervention. From the RAS perspective, the longstanding RAS strategy for the IBM S/390 ® and now the zSeries has provided an excellent foundation for self management. This paper describes the z900 RAS enhancements and how they strengthen the RAS strategy building blocks and provide a basis for autonomic computing.

Reliability, availability, and serviceability (RAS) of the IBM eServer z990

“…This clearing of requests to the L2 requires a reset of the interface. For the single-core processor chip, this is handled in the same manner as in the z900 server [2]. However, since both processor cores share the interface, when either processor requires recovery, the other processor core must also go through recovery.…”

“…For the single-core processor chip, this is handled in the same manner as for the z900 server [2]. For the dual-core processor chip, since both cores share an interface with the L2 cache, both cores must checkstop.…”

“…Physically, the storage structure is hierarchical and spread across all the books. The robust design for the Level 1 and Level 2 caches is carried over from the z900 server [2]. The Level 1 (L1) cache is a parity-protected, store-through cache on the processor chip featuring purge, delete, and relocate capability to recover from cache errors.…”

“…In addition, there would be an increase in the power required and a significant increase in the z990 footprint. These issues were addressed by introducing higher-speed I/O interconnect (eSTI) and I/O cards, extending the internal high-speed HiperSockets* recently introduced in the z900 server [2], increasing the number of channel subsystems (CSS), extending the sharing concept of the Enterprise Systems Connection (ESCON*) multiple image facility (EMIF) to share I/O cards across the logical channel subsystems, and using only the high-density I/O cage introduced in the z900 server [1].…”

Packaging the IBM eServer z990 central electronic complex

“…Figure 6 shows a simplified block diagram of the interconnection of these units within the z990 server. Active redundancy is employed for power supplies and air-moving devices [9]. The z990 introduced two new power requirements.…”