Rate-Adaptive Concatenated Polar-Staircase Codes for Data Center Interconnects

Mehmood, Tayyab; Yankov, Metodi P.; Fisker, A. V.; Gormsen, Kim; Forchhammer, Søren

doi:10.1364/ofc.2020.th1i.6

Cited by 11 publications

(17 citation statements)

References 3 publications

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“…The transmitter is inline with the OIF 400ZR implementation agreement, where a Hamming code of a relatively high fixed rate is used for SD FEC. In this letter, we apply the polar code (PC) proposed as a replacement in [7]. The PC is decoded using cyclic redundancy check (CRC) aided successive cancellation list decoding with a list size of 32 and a CRC length of 16.…”

Section: A Proposed Fecmentioning

confidence: 99%

Block Error Detection Driven Nonlinearity Compensation for Optical Fiber Communications

Yankov

Mehmood

Iqbal

et al. 2021

IEEE Photon. Technol. Lett.

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Section: A Proposed Fecmentioning

confidence: 99%

Block Error Detection Driven Nonlinearity Compensation for Optical Fiber Communications

Yankov

Mehmood

Iqbal

et al. 2021

IEEE Photon. Technol. Lett.

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“…If the requirements of some systems entail the use of a wider range of coding gain and throughput, the VRVTPD design may be considered. But since the area of the VRVTPD design is significantly larger than that of VRPD, concatenated schemes [23], [24] are probably a more viable option.…”

Section: Variable-rate Variable-t Product Decoder (Vrvtpd)mentioning

confidence: 99%

“…Concatenated schemes, using a combination of an inner and an outer code, have been introduced to balance coding gain and complexity: Previous work in this area includes the concatenation of variable-rate outer Reed-Solomon HD codes and an inner repetition code using soft combining for further rate variation [23] as well as the concatenation of a fixed-rate outer HD staircase code and an inner polar code, whose short block lengths can make implementation of variable-rate circuit features practical [24].…”

Section: Introductionmentioning

confidence: 99%

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder

Jain

Fougstedt

Larsson-Edefors

2021

IEEE Trans. Circuits Syst. I

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Variable-rate transceivers, which adapt to the conditions, will be central to energy-efficient communication. However, fiber-optic communication systems with high bit-rate requirements make design of flexible transceivers challenging, since additional circuits needed to orchestrate the flexibility will increase area and degrade speed. We propose a variable-rate VLSI architecture of a forward error correction (FEC) decoder based on hard-decision product codes. Variable shortening of component codes provides a mechanism by which code rate can be varied, the number of iterations offers a knob to control the coding gain, while a key-equation solver module that can swap between error-locator polynomial coefficients provides a means to change error correction capability. Our evaluations based on 28nm netlists show that a variable-rate decoder implementation can offer a net coding gain (NCG) range of 9.96-10.38 dB at a post-FEC bit-error rate of 10 −15 . The decoder achieves throughputs in excess of 400 Gb/s, latencies below 53 ns, and energy efficiencies of 1.14 pJ/bit or less. While the area of the variable-rate decoder is 31% larger than a decoder with a fixed rate, the power dissipation is a mere 5% higher. The variable error correction capability feature increases the NCG range further, to above 10.5 dB, but at a significant area cost.

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“…In order to reduce the complexity of the FEC decoders, the concatenated (inner soft-decision and outer hard-decision code) FEC (CFEC) approach is gaining traction [2], [18]- [21].…”

Section: Introductionmentioning

confidence: 99%

“…Hence, for future 800ZR+ data center interconnects, it is highly desirable to have a low-power, high-performance, and/or rate flexible solution with the same CFEC structure and an error floor below 10 −15 [24]. In [21], a rate flexible CFEC solution was proposed with the same structure as in the 400ZR FEC of [22] but with a different inner code by replacing the Hamming code with rate flexible polar code. The concatenated polar-staircase code (CPSC) offers rate flexibility with near-continuous granularity and 0.35 dB of extra gain when compared with the 400ZR FEC design [21].…”

Section: Introductionmentioning

confidence: 99%

Flexible Multilevel Coding with Concatenated Polar-Staircase Codes for M-QAM

Mehmood

Yankov

Iqbal

et al. 2020

IEEE Trans. Commun.

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In this work, a multilevel coding (MLC) based coded modulation scheme with two degrees of freedom in rate flexibility is proposed and compared with a bit-interleaved coded modulation (BICM) scheme from a performance versus complexity perspective. The proposed MLC scheme is based on a rate flexible inner soft-decision polar code and utilizes an outer hard-decision staircase code structure as in the 400ZR concatenated forward error-correcting code. The performance of the MLC scheme is investigated for a range of inner code lengths, inner decoder list sizes, and signaling with 16 and 64 quadrature amplitude modulation, respectively. The MLC is designed such that a portion of the staircase encoded bits can bypass the inner code. The number of required inner soft-decision decoders can thus be reduced, thereby saving computational complexity. The proposed MLC scheme simultaneously offers up to a 53.7% reduction in the number of inner decoders and up to 0.55 dB of performance improvement when compared with the similar BICM approach.

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Rate-Adaptive Concatenated Polar-Staircase Codes for Data Center Interconnects

Abstract: A rate-adaptive concatenated code, consisting of an outer staircase code and an inner polar code is proposed. Short blocklength inner polar codes offers rate-adaptivity and more than 0.35 dB gain compared to the 400ZR data-center-interconnect error-correcting code.

Cited by 11 publications

References 3 publications

Block Error Detection Driven Nonlinearity Compensation for Optical Fiber Communications

Block Error Detection Driven Nonlinearity Compensation for Optical Fiber Communications

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder

Flexible Multilevel Coding with Concatenated Polar-Staircase Codes for M-QAM

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